Mesa (main): 25 new commits

Thu Jun 10 20:23:42 UTC 2021

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c88eb668141284adc2a04eec9a685fd99af980dc
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Mar 4 15:47:39 2021 +0100

    ir3: Copy propagate immed/const to meta instructions
    
    This is allowed with the new RA, and makes a huge difference in
    preventing extra moves when preferential coloring doesn't work.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a61a9cd65dd52b4bccfb33c3fba7b28a84a1a4e1
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Mar 4 12:21:50 2021 +0100

    ir3: Insert output collects in the main shader
    
    We were inserting them in what was NIR's end block with the "end"
    instruction, which meant that the moves they generated couldn't be
    scheduled with the rest of the last block as part of post-RA scheduling.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa17295ebdd42ab9f6a76ce44f303a99efcf3707
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Mar 4 12:18:44 2021 +0100

    ir3: Add simple CSE pass
    
    RA currently can't handle a live value that's part of a vector and
    introduces extra copies. This was espeically a problem for bary.f, where
    the bary coords were being split and repeatedly re-collected. But this
    could be a problem in other situations as well.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1a1de76e8168bef331eb863a61822f96f43314d
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Apr 26 23:37:04 2021 +0200

    ir3/sched: Consider unused destinations when computing live effect
    
    If an instruction's destination is unused, then we shouldn't penalize
    it. For example, this helps us schedule atomic operations whose results
    aren't read. This works around RA failures when CSE is enabled in some
    robustness2 tests.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba8efeb7fa4a8a1f9b917b6f5ac7df8c2aace52e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Apr 23 13:05:48 2021 +0200

    ir3/sched: Make collects count against tex/sfu limits
    
    In a scenario where there are a lot of texture fetches with constant
    coordinates, this prevents the scheduler from scheduling all the setup
    instructions after the first group of textures has been scheduled
    because they are the only non-syncing thing and scheduling them didn't
    decrease tex_delay. Collects with immed/const sources will turn into
    moves of those sources, so we should treat them the same.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b15c2f30c40155a56a211c2e1c1b6c5fc0368b9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Mar 11 15:00:15 2021 +0100

    ir3/sched: Don't schedule collect early
    
    I don't think there was ever a good reason to do this, but when we start
    folding constants/immediates into collect, this can become actively
    harmful.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=27593cb241c1f571ef172f8db6e91a35028117e3
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Mar 3 15:11:14 2021 +0100

    ir3: Remove right and left copy prop restrictions
    
    This is leftover from the old RA, and inhibits copy propagation
    unnecessarily with the new RA.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f51379d036cefa1a553d087e1b61d2a642c3394
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Apr 26 23:05:53 2021 +0200

    ir3/ra: Add a validation pass
    
    This helps catch tricky-to-debug bugs in RA, or helps rule them out.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ffcb19b9d9fbe902224542047c389a661fbf816
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Feb 19 12:33:49 2021 +0100

    ir3: Rewrite register allocation
    
    Switch to the new SSA-based register allocator.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=df9f41cc027fe959bc71dec90910792e05441079
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Mar 22 15:02:48 2021 +0100

    ir3: Expose occupancy calculation functions
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ac743c333e49c6c91e74073eb8ba01cc6762fc6
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Feb 19 12:14:14 2021 +0100

    ir3: Add pass to lower arrays to SSA
    
    This will be run right after nir->ir3. Even though we have SSA coming
    out of NIR, we still need it for NIR registers, even though we keep the
    original array around to insert false dependencies.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4b5a550ede675748cc2ededd3f19cefcdbc20e1
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Feb 19 12:03:47 2021 +0100

    ir3: Add dominance infrastructure
    
    Mostly lifted from nir.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f3546c9e2de1bdbb0bd76186471022eb66d6163
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri May 14 19:14:47 2021 +0200

    ir3: Remove unused check_src_cond()
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0789395e001a0268c309735110b6e3955ed951e
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Tue Mar 23 18:13:26 2021 +0100

    ir3/postsched: Don't use SSA source information
    
    This was only used for calculating if a source is a tex or SFU
    instruction, which is easily replacable. It's going away with the new
    RA.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c947475533a61c0461a82ec9924ce4279f17e9fc
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon May 17 16:16:55 2021 +0200

    ir3/delay: Delete pre-RA repeat handling
    
    It looks likely that any implementation of (rptN) in ir3 will have to
    actually create (rptN) instructions after RA, which means that this can
    be dropped.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d82add87ede4dc6533f97f7e23e4ba09e1d242
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Feb 19 10:53:08 2021 +0100

    ir3: Rewrite delay calculation
    
    The old delay calculation relied on the SSA information staying around,
    and wouldn't work once we start introducing phi nodes and making
    "normal" values defined in multiple blocks not array regs anymore.
    What's worse is that properly inserting phi nodes when splitting live
    ranges would make that code even more complicated, and this was the last
    place post-RA that actually needed that information.
    
    The new version only compares the physical registers of sources and
    destinations. It works by going backwards up to a maximum number of
    cycles, so it might be slightly slower when the definition is closer but
    should be faster when it is farther away.
    
    To avoid complicating the new method, the old method is kept around, but
    only for pre-RA scheduling and it can therefore be drastically
    simplified as the array case can be dropped.
    
    ir3_delay_calc() is split into a few variants to avoid an explosion of
    boolean arguments in users, especially now that merged_regs now has to
    be passed to it.
    
    The new method is a little more complicated when it comes to handling
    (rptN), because both the assigner and consumer may be (rptN). This adds
    some unit tests for those cases, in addition to dropping the to-SSA code
    in the test harness since it's no longer needed.
    
    Finally, ir3_legalize has to be switched to using physical registers for
    the branch condition. This was the one place where IR3_REG_SSA remained
    after RA.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0823a2d31c995395a8d2567b0c14793e8b569ca
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon May 17 16:38:26 2021 +0200

    ir3: Make branch conditions non-SSA
    
    In particular, make sure they have a physreg assigned. This was the last
    place after RA where SSA registers were created, which won't work with
    the new post-RA delay calculation that relies on the physreg.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc7402b4cf472608f61982c98f79e41bb1970cc7
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Mar 25 15:22:44 2021 +0100

    ir3: Add reg_elems(), reg_elem_size(), and reg_size()
    
    For working with registers in units of half-regs in the new RA.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=890de1a43603c98b5788f9867ff0793f117b5f4b
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Mon Feb 22 15:00:55 2021 +0100

    ir3/delay: Fix full->half and half->full delay
    
    The current compiler never does this, but the new compiler will start to
    in mergeregs mode. There is an extra penalty for this.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ad83f51eb3c089aad0640c2ee6ad6d9477fc2b6
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Feb 19 11:18:02 2021 +0100

    ir3: Add ir3_register::array.base
    
    There were two different approaches I saw in the post-RA code for
    figuring out what regiser range a relative access touched:
    
    1. Use reg->array.offset and reg->array.size. This is wrong in case
       reg->array.offset was non-zero before RA, because array.size is
       the size of the whole array and array.offset has the const offset
       within the array baked in.
    2. Lookup the array from the array ID and use the base + range there.
       This is correct, but won't work with the new RA, where an array might
       not always be assigned to the same register.
    
    This replaces both methods with a new ir3_register::array.base field,
    and switches all the users I could find to it.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=939ee6966f87aa783f43b06ce3e9686ca2caa775
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Fri Mar 5 22:09:41 2021 +0100

    ir3: Improve register printing for SSA
    
    Print the ssa name for array destinations, and handle printing undef SSA
    sources.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=edf23e15eba18f59637e1fcc382024df31cf1594
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Feb 18 17:57:49 2021 +0100

    ir3: Prepare for instructions with multiple destinations
    
    To simplify the pre-RA merge set code and express the result live-range
    splitting in RA, we need to add support for parallel copy instructions,
    and for the merge set code these parallel copies need to be in SSA form.
    Parallel copies have multiple destinations by necessity, but there was
    no way to express this in the existing IR. In particular there was no
    support for marking a register as being a destination, and no support
    for indicating which destination register out of several an SSA source
    refers to. This replaces ir3_register::instr with ir3_register::def and
    re-purposes ir3_register::instr. I haven't propagated this into common
    helpers, like ssa(), because that would vastly increase the amount of
    churn and the number of places that produce such instructions should be
    limited -- only RA will create parallel copies and they will be
    destroyed right after RA. In the future swz will have multiple
    destinations too, but it will only be created after RA via parallel copy
    lowering.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1d724057683e2d624a82fe37f358d8250d73374
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Feb 10 19:49:46 2021 +0100

    ir3: Readd support for translating NIR phi nodes
    
    This is roughly based on the support removed a while ago, but it handles
    sources better by associating each source with a predecessor block.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ef021be4aba42e6caa0826d4952e0beddf0ca18
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Tue May 4 11:11:04 2021 +0200

    ir3: Add ir3_start_block()
    
    Name based on nir_start_block(). A number of places were already
    open-coding this, convert them.
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef4e07a1a27f3f6aaed659d3f84f8b77c9dc2e87
Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Feb 10 19:47:18 2021 +0100

    ir3: Introduce phi and parallelcopy instructions
    
    Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>