Mesa (master): freedreno: Use threadsize calculated by ir3

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 2ecb9700e8408a64ac5512b52c71b6305d3e3740
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ecb9700e8408a64ac5512b52c71b6305d3e3740

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Mar 10 13:42:47 2021 +0100

freedreno: Use threadsize calculated by ir3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9498>

---

 src/gallium/drivers/freedreno/a4xx/fd4_program.c |  2 +-
 src/gallium/drivers/freedreno/a5xx/fd5_compute.c | 17 +++--------------
 src/gallium/drivers/freedreno/a5xx/fd5_program.c |  2 +-
 src/gallium/drivers/freedreno/a6xx/fd6_compute.c |  2 +-
 src/gallium/drivers/freedreno/a6xx/fd6_program.c |  4 ++--
 5 files changed, 8 insertions(+), 19 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_program.c b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
index 99b3b03315f..f5f8ef26099 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_program.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_program.c
@@ -176,7 +176,7 @@ fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
 
 	setup_stages(emit, s);
 
-	fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
+	fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
 
 	/* blob seems to always use constmode currently: */
 	constmode = 1;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
index bb15e552c59..f8b75c9f14d 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
@@ -35,12 +35,10 @@
 
 /* maybe move to fd5_program? */
 static void
-cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
-		const struct pipe_grid_info *info)
+cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
 {
-	const unsigned *local_size = info->block;
 	const struct ir3_info *i = &v->info;
-	enum a3xx_threadsize thrsz;
+	enum a3xx_threadsize thrsz = i->double_threadsize ? FOUR_QUADS : TWO_QUADS;
 	unsigned instrlen = v->instrlen;
 
 	/* if shader is more than 32*16 instructions, don't preload it.  Similar
@@ -49,15 +47,6 @@ cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
 	if (instrlen > 32)
 		instrlen = 0;
 
-	/* maybe the limit should be 1024.. basically if we can't have full
-	 * occupancy, use TWO_QUAD mode to reduce divergence penalty.
-	 */
-	if ((local_size[0] * local_size[1] * local_size[2]) < 512) {
-		thrsz = TWO_QUADS;
-	} else {
-		thrsz = FOUR_QUADS;
-	}
-
 	OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
 	OUT_RING(ring, 0x00000000);        /* SP_SP_CNTL */
 
@@ -128,7 +117,7 @@ fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
 		return;
 
 	if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
-		cs_program_emit(ring, v, info);
+		cs_program_emit(ring, v);
 
 	fd5_emit_cs_state(ctx, ring, v);
 	fd5_emit_cs_consts(v, ring, ctx, info);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index 474499e1d4a..5399e0e3e7e 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -249,7 +249,7 @@ fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 
 	bool do_streamout = (s[VS].v->shader->stream_output.num_outputs > 0);
 
-	fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
+	fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
 
 	pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
 	psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
index 652e2399725..1ba59fd71d9 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_compute.c
@@ -44,7 +44,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
 				struct ir3_shader_variant *v) assert_dt
 {
 	const struct ir3_info *i = &v->info;
-	enum a6xx_threadsize thrsz = THREAD128;
+	enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
 
 	OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
 			.vs_state = true,
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index edf121ba68c..00b4f66acda 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -332,7 +332,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
 
 	bool sample_shading = fs->per_samp | key->sample_shading;
 
-	fssz = THREAD128;
+	fssz = fs->info.double_threadsize ? THREAD128 : THREAD64;
 
 	pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
 	psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
@@ -709,7 +709,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_context *ctx,
 	OUT_RING(ring, 0xfc);              /* XXX */
 
 	OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
-	OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(THREAD128) |
+	OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(fssz) |
 			       COND(enable_varyings, A6XX_HLSQ_FS_CNTL_0_VARYINGS));
 
 	OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);