Mesa (staging/21.3): radeonsi: fix 2 issues with depth_cleared_level_mask
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Thu Nov 4 22:59:17 UTC 2021
Module: Mesa
Branch: staging/21.3
Commit: 99c9bbfb3828714b6da030cac40ed16224ace3c9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99c9bbfb3828714b6da030cac40ed16224ace3c9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Oct 29 13:27:54 2021 -0400
radeonsi: fix 2 issues with depth_cleared_level_mask
- Unset depth_cleared_level_mask for non-clear blits. Set the flag after
the clear, so that we don't have to check blitter_running.
- Set depth_cleared_level_mask only when we set depth_clear_value.
Fixes: ff8a930cf7de6aa7 - radeonsi: add _once suffix to depth_cleared_level_mask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603>
(cherry picked from commit 5d3aea49b806322393c3275d550f4e4eaef3cca3)
---
.pick_status.json | 2 +-
src/gallium/drivers/radeonsi/si_clear.c | 9 ++++++---
src/gallium/drivers/radeonsi/si_pipe.h | 2 +-
src/gallium/drivers/radeonsi/si_state_draw.cpp | 2 +-
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index 7b8e2c1af78..440802f58dc 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -148,7 +148,7 @@
"description": "radeonsi: fix 2 issues with depth_cleared_level_mask",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": "ff8a930cf7de6aa77c350ac9b010719d40f18e4d"
},
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index b8cf49a6b47..a5a5decc02b 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -802,6 +802,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_value = si_get_htile_clear_value(zstex, depth);
*buffers &= ~PIPE_CLEAR_DEPTH;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
update_db_depth_clear = true;
}
} else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
@@ -811,6 +812,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_value = si_get_htile_clear_value(zstex, depth);
*buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
zstex->stencil_cleared_level_mask |= BITFIELD_BIT(level);
update_db_depth_clear = true;
update_db_stencil_clear = true;
@@ -875,6 +877,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_types |= SI_CLEAR_TYPE_HTILE;
*buffers &= ~PIPE_CLEAR_DEPTH;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
update_db_depth_clear = true;
}
} else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
@@ -888,6 +891,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_types |= SI_CLEAR_TYPE_HTILE;
*buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
zstex->stencil_cleared_level_mask |= BITFIELD_BIT(level);
update_db_depth_clear = true;
update_db_stencil_clear = true;
@@ -913,6 +917,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
clear_types |= SI_CLEAR_TYPE_HTILE;
*buffers &= ~PIPE_CLEAR_DEPTH;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
update_db_depth_clear = true;
} else if (htile_size &&
!(*buffers & PIPE_CLEAR_DEPTH) &&
@@ -970,9 +975,6 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
else if (!util_format_has_stencil(util_format_description(zsbuf->format)))
buffers &= ~PIPE_CLEAR_STENCIL;
- if (buffers & PIPE_CLEAR_DEPTH)
- zstex->depth_cleared_level_mask |= BITFIELD_BIT(zsbuf->u.tex.level);
-
si_fast_clear(sctx, &buffers, color, depth, stencil);
if (!buffers)
return; /* all buffers have been cleared */
@@ -1055,6 +1057,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
sctx->db_depth_clear = false;
sctx->db_depth_disable_expclear = false;
zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(zsbuf->u.tex.level);
+ zstex->depth_cleared_level_mask |= BITFIELD_BIT(zsbuf->u.tex.level);
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 1cd347ab751..d9a6abec609 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -360,7 +360,7 @@ struct si_texture {
float depth_clear_value[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
- uint16_t depth_cleared_level_mask; /* track if it was cleared (not 100% accurate) */
+ uint16_t depth_cleared_level_mask; /* track if it's cleared (can be false negative) */
uint16_t stencil_cleared_level_mask; /* if it was cleared at least once */
uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index e090244ae9c..8debad2d66e 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -2482,7 +2482,7 @@ static void si_draw(struct pipe_context *ctx,
sctx->num_prim_restart_calls += num_draws;
}
- if (!sctx->blitter_running && sctx->framebuffer.state.zsbuf) {
+ if (sctx->framebuffer.state.zsbuf) {
struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
zstex->depth_cleared_level_mask &= ~BITFIELD_BIT(sctx->framebuffer.state.zsbuf->u.tex.level);
}
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