Mesa (staging/21.3): radeonsi: fix a typo preventing a fast depth-stencil clear

[GitLab Mirror]

Module: Mesa
Branch: staging/21.3
Commit: 8794b65263e93b130b1ae66e85ed37917aa67d4a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8794b65263e93b130b1ae66e85ed37917aa67d4a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Oct 30 11:43:42 2021 -0400

radeonsi: fix a typo preventing a fast depth-stencil clear

Fixes: 9defe8aca953b69615728c8 - radeonsi: implement fast Z/S clears using clear_buffer on HTILE

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13603>
(cherry picked from commit 74adf22a0aeeaf5f63748394d2da0337b04b1526)

---

 .pick_status.json                       | 2 +-
 src/gallium/drivers/radeonsi/si_clear.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 440802f58dc..27378833c51 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -112,7 +112,7 @@
         "description": "radeonsi: fix a typo preventing a fast depth-stencil clear",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "9defe8aca953b69615728c84d8ff6ed51bdded00"
     },
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index a5a5decc02b..aa73131bb24 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -805,7 +805,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                   zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                   update_db_depth_clear = true;
                }
-            } else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
+            } else if ((*buffers & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL) {
                if (si_can_fast_clear_depth(zstex, level, depth, *buffers) &&
                    si_can_fast_clear_stencil(zstex, level, stencil, *buffers)) {
                   /* Combined Z+S clear. */
@@ -880,7 +880,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                update_db_depth_clear = true;
             }
-         } else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
+         } else if ((*buffers & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL) {
             if (htile_size &&
                 si_can_fast_clear_depth(zstex, level, depth, *buffers) &&
                 si_can_fast_clear_stencil(zstex, level, stencil, *buffers)) {