Mesa (main): radeonsi: unify GFX9_VSGS_NUM_USER_SGPR and GFX9_TESGS_NUM_USER_SGPR

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Module: Mesa
Branch: main
Commit: 5a5263d65deed894041a43c450d1636f6a0545e1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a5263d65deed894041a43c450d1636f6a0545e1

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Nov  7 00:04:31 2021 -0400

radeonsi: unify GFX9_VSGS_NUM_USER_SGPR and GFX9_TESGS_NUM_USER_SGPR

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>

---

 src/gallium/drivers/radeonsi/gfx10_shader_ngg.c   | 4 ++--
 src/gallium/drivers/radeonsi/si_shader.c          | 4 ++--
 src/gallium/drivers/radeonsi/si_shader.h          | 3 +--
 src/gallium/drivers/radeonsi/si_state_draw.cpp    | 2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.cpp | 8 ++++----
 5 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
index b5369faf6ec..64c1b3d5b2a 100644
--- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
+++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
@@ -1248,10 +1248,10 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi)
       if (shader->selector->num_vbos_in_user_sgprs) {
          vgpr = 8 + SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4;
       } else {
-         vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR + 1;
+         vgpr = 8 + GFX9_GS_NUM_USER_SGPR + 1;
       }
    } else {
-      vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
+      vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
    }
 
    val = LLVMBuildLoad(builder, new_vgpr0, "");
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index c19790ae293..98170796d6d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -571,7 +571,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
             /* For the NGG cull shader, add 1 SGPR to hold
              * the vertex buffer pointer.
              */
-            num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR + 1;
+            num_user_sgprs = GFX9_GS_NUM_USER_SGPR + 1;
 
             if (shader->selector->num_vbos_in_user_sgprs) {
                assert(num_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST);
@@ -579,7 +579,7 @@ void si_init_shader_args(struct si_shader_context *ctx, bool ngg_cull_shader)
                   SI_SGPR_VS_VB_DESCRIPTOR_FIRST + shader->selector->num_vbos_in_user_sgprs * 4;
             }
          } else if (ctx->stage == MESA_SHADER_TESS_EVAL && ngg_cull_shader) {
-            num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+            num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
          } else {
             num_user_sgprs = SI_NUM_VS_STATE_RESOURCE_SGPRS;
          }
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h
index bc27e82e696..a6292f9b397 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -211,8 +211,7 @@ enum
 
    /* GS limits */
    GFX6_GS_NUM_USER_SGPR = SI_NUM_RESOURCE_SGPRS,
-   GFX9_VSGS_NUM_USER_SGPR = SI_VS_NUM_USER_SGPR,
-   GFX9_TESGS_NUM_USER_SGPR = SI_TES_NUM_USER_SGPR,
+   GFX9_GS_NUM_USER_SGPR = MAX2(SI_VS_NUM_USER_SGPR, SI_TES_NUM_USER_SGPR),
    SI_GSCOPY_NUM_USER_SGPR = SI_NUM_VS_STATE_RESOURCE_SGPRS,
 
    /* PS only */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index c721ce5c532..38bcce94056 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -1863,7 +1863,7 @@ static bool si_upload_and_prefetch_VB_descriptors(struct si_context *sctx,
             if (HAS_TESS)
                sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
             else if (HAS_GS)
-               sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
+               sh_dw_offset = GFX9_GS_NUM_USER_SGPR;
          }
 
          radeon_set_sh_reg(sh_base + sh_dw_offset * 4,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index dede48d9220..358808f3b8e 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -910,9 +910,9 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
 
       unsigned num_user_sgprs;
       if (es_stage == MESA_SHADER_VERTEX)
-         num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
+         num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
       else
-         num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+         num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
 
       if (sscreen->info.chip_class >= GFX10) {
          si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
@@ -1178,12 +1178,12 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
          num_user_sgprs =
             SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
       } else {
-         num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
+         num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
       }
    } else {
       assert(es_stage == MESA_SHADER_TESS_EVAL);
       es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
-      num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+      num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
 
       if (es_enable_prim_id || gs_info->uses_primid)
          break_wave_at_eoi = true;