Mesa (main): radeonsi: add dcc_msaa option to enable DCC for MSAA

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Module: Mesa
Branch: main
Commit: 901697654ac9ce98e0ae1d7a5ea6d53404a7452a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=901697654ac9ce98e0ae1d7a5ea6d53404a7452a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Fri Nov  5 19:34:03 2021 -0400

radeonsi: add dcc_msaa option to enable DCC for MSAA

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>

---

 src/gallium/drivers/radeonsi/si_debug_options.h | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c          | 7 +++++--
 src/gallium/drivers/radeonsi/si_texture.c       | 3 +--
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_debug_options.h b/src/gallium/drivers/radeonsi/si_debug_options.h
index 2eda68e06f7..7aec64b614a 100644
--- a/src/gallium/drivers/radeonsi/si_debug_options.h
+++ b/src/gallium/drivers/radeonsi/si_debug_options.h
@@ -16,6 +16,7 @@ OPT_BOOL(disable_sam, false, "Disable Smart Access Memory.")
 OPT_BOOL(fp16, false, "Enable FP16 for mediump.")
 OPT_INT(tc_max_cpu_storage_size, 0, "Enable the CPU storage for pipelined buffer uploads in TC.")
 OPT_BOOL(force_use_fma32, false, "Force use fma32 instruction for GPU family newer than gfx9")
+OPT_BOOL(dcc_msaa, false, "Enable DCC for MSAA")
 
 #undef OPT_BOOL
 #undef OPT_INT
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 4a94415e06d..f24c635808b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1289,8 +1289,11 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
    /* Only set this for the cases that are known to work, which are:
     * - GFX9 if bpp >= 4 (in bytes)
     */
-   if (sscreen->info.chip_class == GFX9) {
-      for (unsigned bpp_log2 = util_logbase2(4); bpp_log2 <= util_logbase2(16); bpp_log2++)
+   if (sscreen->info.chip_class >= GFX10) {
+      memset(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp, true,
+             sizeof(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp));
+   } else if (sscreen->info.chip_class == GFX9) {
+      for (unsigned bpp_log2 = util_logbase2(1); bpp_log2 <= util_logbase2(16); bpp_log2++)
          sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true;
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index ce0f113b6cb..728b0777dcd 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -243,8 +243,7 @@ static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surfac
 
       case GFX10:
       case GFX10_3:
-         /* DCC causes corruption with MSAA. */
-         if (ptex->nr_storage_samples >= 2)
+         if (ptex->nr_storage_samples >= 2 && !sscreen->options.dcc_msaa)
             flags |= RADEON_SURF_DISABLE_DCC;
          break;