Mesa (main): pan/bi: Forbid unaligned staging registers on Valhall

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Module: Mesa
Branch: main
Commit: b8ba909ca6b080f156f773f3ca8c9ed3d18c4ae9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8ba909ca6b080f156f773f3ca8c9ed3d18c4ae9

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu Nov  4 19:08:36 2021 -0400

pan/bi: Forbid unaligned staging registers on Valhall

Would've saved me some debugging with the computerator. I keep
forgetting about this nuance. Enforce it in the assembler.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13802>

---

 src/panfrost/bifrost/valhall/asm.py                  | 2 ++
 src/panfrost/bifrost/valhall/test/negative-cases.txt | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/src/panfrost/bifrost/valhall/asm.py b/src/panfrost/bifrost/valhall/asm.py
index ae3e4fa355d..7ad678767b6 100644
--- a/src/panfrost/bifrost/valhall/asm.py
+++ b/src/panfrost/bifrost/valhall/asm.py
@@ -221,6 +221,8 @@ def parse_asm(line):
         base = regs[0]
         die_if(any([reg != (base + i) for i, reg in enumerate(regs)]),
                 'Expected consecutive staging registers, got {op}')
+        die_if(sr_count > 1 and (base % 2) != 0,
+                'Consecutive staging registers must be aligned to a register pair')
 
         if sr.count == 0:
             modifier_map["staging_register_count"] = sr_count
diff --git a/src/panfrost/bifrost/valhall/test/negative-cases.txt b/src/panfrost/bifrost/valhall/test/negative-cases.txt
index 1898c94ce79..71e12aab8c0 100644
--- a/src/panfrost/bifrost/valhall/test/negative-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/negative-cases.txt
@@ -37,3 +37,9 @@ IADD.u32.ts r0, tls_ptr, wls_ptr
 IADD.u32.ts r0, tls_ptr, tls_ptr_hi
 IADD.u32.id r0, tls_ptr, tls_ptr_hi
 IADD.u32.id r0, tls_ptr, 0x40490FDB
+
+# If an instruction accesses multiple staging registers, they must be aligned
+# to a register pair.
+LOAD.i32.unsigned.slot0.wait0 @r1:r2, `r0, offset:0
+STORE.i32.slot0.reconverge @r3:r4:r5, `r2, offset:0
+STORE.i96.vary.slot0.return @r1:r2:r3:r4, `r4, offset:0