Mesa (main): intel/compiler: Fix instruction size written calculation

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 75c73fcdc4282d6b809dd590cb50c584738490c2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=75c73fcdc4282d6b809dd590cb50c584738490c2

Author: Sagar Ghuge <sagar.ghuge at intel.com>
Date:   Wed Oct 13 11:14:43 2021 -0700

intel/compiler: Fix instruction size written calculation

We are always aligning to REG_SIZE but when we have payload sources less
than REG_SIZE, size written is miscalculated.

Signed-off-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

---

 src/intel/compiler/brw_fs_builder.h | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h
index f156cb3e5b3..ce340f41de6 100644
--- a/src/intel/compiler/brw_fs_builder.h
+++ b/src/intel/compiler/brw_fs_builder.h
@@ -771,9 +771,8 @@ namespace brw {
          inst->header_size = header_size;
          inst->size_written = header_size * REG_SIZE;
          for (unsigned i = header_size; i < sources; i++) {
-            inst->size_written +=
-               ALIGN(dispatch_width() * type_sz(src[i].type) * dst.stride,
-                     REG_SIZE);
+            inst->size_written += dispatch_width() * type_sz(src[i].type) *
+                                  dst.stride;
          }
 
          return inst;