Mesa (main): intel/compiler: Demote sampler params to 16-bit for CMS/UMS/MCS

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Tue Nov 23 07:08:04 UTC 2021


Module: Mesa
Branch: main
Commit: dfe0ba908009b075278cae5ee0eb53e8e5396c9a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfe0ba908009b075278cae5ee0eb53e8e5396c9a

Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Jul  7 23:32:51 2020 -0700

intel/compiler: Demote sampler params to 16-bit for CMS/UMS/MCS

Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>

---

 src/intel/compiler/brw_fs.cpp | 39 +++++++++++++++++++++++++++++++++------
 1 file changed, 33 insertions(+), 6 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 4101b7830e4..d45a317b66e 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5616,7 +5616,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
 }
 
 static unsigned
-get_sampler_msg_payload_type_bit_size(const fs_reg *src)
+get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo,
+                                      opcode op, const fs_reg *src)
 {
    unsigned src_type_size = 0;
 
@@ -5633,13 +5634,39 @@ get_sampler_msg_payload_type_bit_size(const fs_reg *src)
    assert(src_type_size == 2 || src_type_size == 4);
 
 #ifndef NDEBUG
-   /* Make sure all sources agree. */
-   for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
-      assert(src[i].file == BAD_FILE ||
-             brw_reg_type_to_size(src[i].type) == src_type_size);
+   /* Make sure all sources agree. On gfx12 this doesn't hold when sampling
+    * compressed multisampled surfaces. There the payload contains MCS data
+    * which is already in 16-bits unlike the other parameters that need forced
+    * conversion.
+    */
+   if (devinfo->verx10 < 125 ||
+       (op != SHADER_OPCODE_TXF_CMS_W &&
+        op != SHADER_OPCODE_TXF_CMS)) {
+      for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) {
+         assert(src[i].file == BAD_FILE ||
+                brw_reg_type_to_size(src[i].type) == src_type_size);
+      }
    }
 #endif
 
+   if (devinfo->verx10 < 125)
+      return src_type_size * 8;
+
+   /* Force conversion from 32-bit sources to 16-bit payload. From the XeHP Bspec:
+    * 3D and GPGPU Programs - Shared Functions - 3D Sampler - Messages - Message
+    * Format [GFX12:HAS:1209977870] *
+    *
+    *  ld2dms_w       SIMD8H and SIMD16H Only
+    *  ld_mcs         SIMD8H and SIMD16H Only
+    *  ld2dms         REMOVEDBY(GEN:HAS:1406788836)
+    */
+
+   if (op == SHADER_OPCODE_TXF_CMS_W ||
+       op == SHADER_OPCODE_TXF_CMS ||
+       op == SHADER_OPCODE_TXF_UMS ||
+       op == SHADER_OPCODE_TXF_MCS)
+      src_type_size = 2;
+
    return src_type_size * 8;
 }
 
@@ -5666,7 +5693,7 @@ lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
 
    if (devinfo->ver >= 7) {
       const unsigned msg_payload_type_bit_size =
-         get_sampler_msg_payload_type_bit_size(inst->src);
+         get_sampler_msg_payload_type_bit_size(devinfo, op, inst->src);
 
       /* 16-bit payloads are available only on gfx11+ */
       assert(msg_payload_type_bit_size != 16 || devinfo->ver >= 11);



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