Mesa (main): radv,aco: remove nir_intrinsic_load_layer_id

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Module: Mesa
Branch: main
Commit: 61a3e7524219a824fd2223a5de69959e3f5a680e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=61a3e7524219a824fd2223a5de69959e3f5a680e

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Wed Oct  6 14:06:59 2021 +0200

radv,aco: remove nir_intrinsic_load_layer_id

This was never used because the layer ID isn't a system value.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13243>

---

 src/amd/compiler/aco_instruction_selection.cpp       | 14 ++------------
 src/amd/compiler/aco_instruction_selection_setup.cpp |  1 -
 src/amd/vulkan/radv_shader_info.c                    |  4 ----
 3 files changed, 2 insertions(+), 17 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 78ef6aa691b..1ee9b227811 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -8023,18 +8023,8 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
       break;
    }
    case nir_intrinsic_load_view_index: {
-      if (ctx->stage.has(SWStage::VS) || ctx->stage.has(SWStage::GS) ||
-          ctx->stage.has(SWStage::TCS) || ctx->stage.has(SWStage::TES)) {
-         Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
-         bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
-         break;
-      }
-      FALLTHROUGH;
-   }
-   case nir_intrinsic_load_layer_id: {
-      unsigned idx = nir_intrinsic_base(instr);
-      bld.vintrp(aco_opcode::v_interp_mov_f32, Definition(get_ssa_temp(ctx, &instr->dest.ssa)),
-                 Operand::c32(2u), bld.m0(get_arg(ctx, ctx->args->ac.prim_mask)), idx, 0);
+      Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
+      bld.copy(Definition(dst), Operand(get_arg(ctx, ctx->args->ac.view_index)));
       break;
    }
    case nir_intrinsic_load_frag_coord: {
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 5c85d1f3099..c2bf55e5960 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -631,7 +631,6 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_intrinsic_load_frag_coord:
                case nir_intrinsic_load_frag_shading_rate:
                case nir_intrinsic_load_sample_pos:
-               case nir_intrinsic_load_layer_id:
                case nir_intrinsic_load_local_invocation_id:
                case nir_intrinsic_load_local_invocation_index:
                case nir_intrinsic_load_subgroup_invocation:
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index f7c063de748..f72ea1dad64 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -222,10 +222,6 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
       if (nir->info.stage == MESA_SHADER_FRAGMENT)
          info->ps.layer_input = true;
       break;
-   case nir_intrinsic_load_layer_id:
-      if (nir->info.stage == MESA_SHADER_FRAGMENT)
-         info->ps.layer_input = true;
-      break;
    case nir_intrinsic_load_invocation_id:
       info->uses_invocation_id = true;
       break;