Mesa (staging/21.2): iris: Add missed tile flush flag

[GitLab Mirror]

Module: Mesa
Branch: staging/21.2
Commit: 47fe7f13c43c67a378f23ddafae1d7cc8e72ba0d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=47fe7f13c43c67a378f23ddafae1d7cc8e72ba0d

Author: Mykhailo Skorokhodov <mykhailo.skorokhodov at globallogic.com>
Date:   Wed Sep 22 16:03:23 2021 +0300

iris: Add missed tile flush flag

Without adding `PIPE_CONTROL_TILE_CACHE_FLUSH` into `iris_emit_pipe_control`
gen12+ (UHD 750 in my case) has issues with textures.

Related-to: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5029
Fixes: c85ea824('iris: reduce redundant tile cache flushes')

Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov at globallogic.com>
Reviewed-by: Felix DeGrood <felix.j.degrood at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12979>
(cherry picked from commit 0523607ebb108d8c90bbda9c6564b66a0a6250e6)

---

 .pick_status.json                            | 2 +-
 src/gallium/drivers/iris/iris_pipe_control.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 3409c2491da..29f5a0593b5 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -85,7 +85,7 @@
         "description": "iris: Add missed tile flush flag",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "c85ea824bcab971dc2d9052b5dc937ee4b139cf5"
     },
diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index 97689513b72..0f67b63ad56 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -349,7 +349,8 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
 
    if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_FRAMEBUFFER)) {
       bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
-              PIPE_CONTROL_RENDER_TARGET_FLUSH;
+              PIPE_CONTROL_RENDER_TARGET_FLUSH |
+              PIPE_CONTROL_TILE_CACHE_FLUSH;
    }
 
    for (int i = 0; i < IRIS_BATCH_COUNT; i++) {