Mesa (staging/21.2): iris: Tile cache flush for depth before fast clear

[GitLab Mirror]

Module: Mesa
Branch: staging/21.2
Commit: fff5f4708987a901794b70c2d158b7e83b474429
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fff5f4708987a901794b70c2d158b7e83b474429

Author: Nanley Chery <nanley.g.chery at intel.com>
Date:   Tue Jun 22 10:24:31 2021 -0700

iris: Tile cache flush for depth before fast clear

Instead of doing a tile cache flush after slow clears or when the clear
value changes, do it before every fast clear of a HIZ_CCS_WT surface.
This agrees with the Bspec.

Fixes: c85ea824bca ("iris: reduce redundant tile cache flushes")
Reviewed-by: Felix DeGrood <felix.j.degrood at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
(cherry picked from commit d7e836443a530bfb50fc1333311b00e2514e1051)

---

 .pick_status.json                     |  2 +-
 src/gallium/drivers/iris/iris_clear.c | 22 ++++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 29f5a0593b5..95c9a7552d7 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -2713,7 +2713,7 @@
         "description": "iris: Tile cache flush for depth before fast clear",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": "c85ea824bcab971dc2d9052b5dc937ee4b139cf5"
     },
diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index a59ba735cbc..77f0b8c44fa 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -494,8 +494,6 @@ fast_clear_depth(struct iris_context *ice,
                           ISL_AUX_OP_FULL_RESOLVE, false);
             iris_resource_set_aux_state(ice, res, res_level, layer, 1,
                                         ISL_AUX_STATE_RESOLVED);
-            iris_emit_pipe_control_flush(batch, "hiz op: post depth resolve",
-                                         PIPE_CONTROL_TILE_CACHE_FLUSH);
          }
       }
       const union isl_color_value clear_value = { .f32 = {depth, } };
@@ -503,6 +501,23 @@ fast_clear_depth(struct iris_context *ice,
       update_clear_depth = true;
    }
 
+   if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
+      /* From Bspec 47010 (Depth Buffer Clear):
+       *
+       *    Since the fast clear cycles to CCS are not cached in TileCache,
+       *    any previous depth buffer writes to overlapping pixels must be
+       *    flushed out of TileCache before a succeeding Depth Buffer Clear.
+       *    This restriction only applies to Depth Buffer with write-thru
+       *    enabled, since fast clears to CCS only occur for write-thru mode.
+       *
+       * There may have been a write to this depth buffer. Flush it from the
+       * tile cache just in case.
+       */
+      iris_emit_pipe_control_flush(batch, "hiz_ccs_wt: before fast clear",
+                                   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+                                   PIPE_CONTROL_TILE_CACHE_FLUSH);
+   }
+
    for (unsigned l = 0; l < box->depth; l++) {
       enum isl_aux_state aux_state =
          iris_resource_get_aux_state(res, level, box->z + l);
@@ -610,8 +625,7 @@ clear_depth_stencil(struct iris_context *ice,
    blorp_batch_finish(&blorp_batch);
    iris_batch_sync_region_end(batch);
 
-   iris_flush_and_dirty_for_history(ice, batch, res,
-                                    PIPE_CONTROL_TILE_CACHE_FLUSH,
+   iris_flush_and_dirty_for_history(ice, batch, res, 0,
                                     "cache history: post slow ZS clear");
 
    if (clear_depth && z_res) {