Mesa (main): intel/nir: Lower 8 and 16-bit bitwise unops

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 69b5424ea4542a3f340fc49960a7477d8fb57675
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69b5424ea4542a3f340fc49960a7477d8fb57675

Author: Jason Ekstrand <jason.ekstrand at collabora.com>
Date:   Fri Apr  8 15:17:33 2022 -0500

intel/nir: Lower 8 and 16-bit bitwise unops

Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15829>

---

 src/intel/compiler/brw_nir.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 9af4201e290..f705e361070 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -648,6 +648,21 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data)
    switch (instr->type) {
    case nir_instr_type_alu: {
       nir_alu_instr *alu = nir_instr_as_alu(instr);
+      switch (alu->op) {
+      case nir_op_bit_count:
+      case nir_op_ufind_msb:
+      case nir_op_ifind_msb:
+      case nir_op_find_lsb:
+         /* These are handled specially because the destination is always
+          * 32-bit and so the bit size of the instruction is given by the
+          * source.
+          */
+         assert(alu->src[0].src.is_ssa);
+         return alu->src[0].src.ssa->bit_size == 32 ? 0 : 32;
+      default:
+         break;
+      }
+
       assert(alu->dest.dest.is_ssa);
       if (alu->dest.dest.ssa.bit_size >= 32)
          return 0;