Mesa (main): pan/va: Identify LEA_TEX_IMM table
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Fri Feb 18 16:13:55 UTC 2022
Module: Mesa
Branch: main
Commit: c2178d09d073b8c8408b9840ef9073079db6ccfc
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2178d09d073b8c8408b9840ef9073079db6ccfc
Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date: Thu Feb 17 14:39:17 2022 -0500
pan/va: Identify LEA_TEX_IMM table
Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15069>
---
src/panfrost/bifrost/valhall/ISA.xml | 4 ++--
src/panfrost/bifrost/valhall/test/assembler-cases.txt | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 16558359393..5ab5eae2f7a 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -780,7 +780,7 @@
<imm name="table" start="16" size="4"/>
</ins>
- <ins name="LEA_IMAGE_IMM" title="Load effective address of image texel" opcode="0x67" unit="LS">
+ <ins name="LEA_TEX_IMM" title="Load effective address of image texel" opcode="0x67" unit="LS">
<desc>
Load the effective address of a texel from the image specified with the
given immediate index. Returns three staging register: the low/high
@@ -798,8 +798,8 @@
<imm name="unk" start="36" size="4"/>
<src>X/Y coordinates (16:16)</src>
<src>Z/W coordinates (16:16)</src>
+ <imm name="table" start="16" size="4"/>
<imm name="index" start="20" size="4"/>
- <imm name="unk2" start="16" size="4"/>
</ins>
<ins name="LD_BUFFER.i8" title="Global memory load" opcode="0x6a" opcode2="0" unit="LS">
diff --git a/src/panfrost/bifrost/valhall/test/assembler-cases.txt b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
index 6ab27974b82..6ea5cb8874f 100644
--- a/src/panfrost/bifrost/valhall/test/assembler-cases.txt
+++ b/src/panfrost/bifrost/valhall/test/assembler-cases.txt
@@ -111,8 +111,8 @@ c0 01 00 00 00 c4 10 51 IADD_IMM.i32.reconverge r4, 0x0, #0x1
44 00 46 32 28 40 71 78 ST_CVT.v4.f32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 34 28 40 71 78 ST_CVT.v4.s32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
44 00 46 36 28 40 71 78 ST_CVT.v4.u32.slot0.return @r0:r1:r2:r3, `r4, r0, `r6, unk:0x2
-7c c0 12 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x1, unk2:0x2
-7c c0 02 00 26 84 67 00 LEA_IMAGE_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, index:0x0, unk2:0x2
+7c c0 12 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x1
+7c c0 02 00 26 84 67 00 LEA_TEX_IMM.slot0 @r4:r5:r6, `r60, 0x0, unk:0x2, table:0x2, index:0x0
82 81 00 28 f4 82 6a 00 LD_BUFFER.i64.unsigned.slot0 @r2:r3, u2, u1
80 81 00 68 f4 80 6a 00 LD_BUFFER.i64.unsigned.slot1 @r0:r1, u0, u1
84 81 00 a8 f4 a6 6a 00 LD_BUFFER.i64.unsigned.slot2 @r38:r39, u4, u1
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