Mesa (main): pan/va: Fix definitions of TEX_SINGLE and TEX_FETCH

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Module: Mesa
Branch: main
Commit: eee6dad0c97960d98f5785997e1e42ba583ba40b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eee6dad0c97960d98f5785997e1e42ba583ba40b

Author: Alyssa Rosenzweig <alyssa at collabora.com>
Date:   Thu Feb 17 14:05:18 2022 -0500

pan/va: Fix definitions of TEX_SINGLE and TEX_FETCH

Fix the definitions of the basic texturing instructions. In particular, a
register format and a write mask were previously missing, as well as incorrect
handling of staging registers.

Signed-off-by: Alyssa Rosenzweig <alyssa at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

---

 src/panfrost/bifrost/valhall/ISA.xml    | 95 +++++++++++++++++++++++++++------
 src/panfrost/bifrost/valhall/valhall.py | 14 +++++
 2 files changed, 93 insertions(+), 16 deletions(-)

diff --git a/src/panfrost/bifrost/valhall/ISA.xml b/src/panfrost/bifrost/valhall/ISA.xml
index 30728e033e3..172eb86aeca 100644
--- a/src/panfrost/bifrost/valhall/ISA.xml
+++ b/src/panfrost/bifrost/valhall/ISA.xml
@@ -518,6 +518,50 @@
     <value>sr7</value>
   </enum>
 
+  <enum name="Staging register write count" implied="true">
+    <value>write1</value>
+    <value>write2</value>
+    <value>write3</value>
+    <value>write4</value>
+    <value>write5</value>
+    <value>write6</value>
+    <value>write7</value>
+    <value>write8</value>
+  </enum>
+
+  <enum name="Write mask">
+    <reserved/>
+    <value>r</value>
+    <value>g</value>
+    <value>rg</value>
+    <value>b</value>
+    <value>rb</value>
+    <value>gb</value>
+    <value>rgb</value>
+    <value>a</value>
+    <value>ra</value>
+    <value>ga</value>
+    <value>rga</value>
+    <value>ba</value>
+    <value>rba</value>
+    <value>gba</value>
+    <value default="true">rgba</value>
+  </enum>
+
+  <enum name="Register type">
+    <desc>Unsized type, part of a register format.</desc>
+    <reserved/>
+    <value name="Float">f</value>
+    <value name="Unsigned">u</value>
+    <value name="Signed">s</value>
+  </enum>
+
+  <enum name="Register width">
+    <desc>Untyped size, part of a register format.</desc>
+    <value>16</value>
+    <value>32</value>
+  </enum>
+
   <enum name="Vector size">
     <desc>Number of channels loaded/stored for general memory access.</desc>
     <value default="true" desc="Scalar">none</value>
@@ -1972,28 +2016,46 @@
 
   <ins name="TEX_FETCH" title="Texel fetch" opcode="0x125" unit="T">
     <desc>Unfiltered textured instruction.</desc>
-    <sr read="true"/>
-    <sr write="true" count="4"/>
-    <mod name="explicit_offset" start="11" size="1"/>
-    <mod name="dimension" start="28" size="2"/>
-    <mod name="skip" start="39" size="1"/>
-    <sr_count/>
     <slot/>
+    <skip/>
+    <register_type/>
+    <register_width/>
+    <write_mask/>
+    <dimension/>
+    <wide_indices/>
+    <array_enable/>
+    <texel_offset/>
+
+    <!-- Leave secondary_register_width as 0 -->
+    <sr_count/>
+    <sr_write_count/>
+
+    <sr write="true" flags="false"/>
+    <sr read="true" flags="false"/>
     <src>Image to read from</src>
   </ins>
 
-  <ins name="TEX" title="Texture load" opcode="0x128" unit="T">
+  <ins name="TEX_SINGLE" title="Texture load" opcode="0x128" unit="T">
     <desc>Ordinary texturing instruction using a sampler.</desc>
-    <sr read="true"/>
-    <sr write="true" count="4"/>
-    <src>Image to read from</src>
-    <mod name="explicit_offset" start="11" size="1"/>
-    <mod name="shadow" start="12" size="1"/>
-    <mod name="lod_mode" start="13" size="3"/>
-    <mod name="dimension" start="28" size="2"/>
-    <mod name="skip" start="39" size="1"/>
-    <sr_count/>
     <slot/>
+    <skip/>
+    <register_type/>
+    <register_width/>
+    <write_mask/>
+    <dimension/>
+    <wide_indices/>
+    <array_enable/>
+    <texel_offset/>
+    <shadow/>
+    <lod_mode/>
+
+    <!-- Leave secondary_register_width as 0 -->
+    <sr_count/>
+    <sr_write_count/>
+
+    <sr write="true" flags="false"/>
+    <sr read="true" flags="false"/>
+    <src>Image to read from</src>
   </ins>
 
   <ins name="TODO.VAR_TEX" title="Fused varying-texturing" opcode="0x130" unit="VT">
@@ -2005,6 +2067,7 @@
     <mod name="dimension" start="28" size="2"/>
     <mod name="skip" start="39" size="1"/>
     <slot/>
+    <sr_write_count/>
     <src>Image to read from</src>
   </ins>
 
diff --git a/src/panfrost/bifrost/valhall/valhall.py b/src/panfrost/bifrost/valhall/valhall.py
index 32fa00559e4..343c9de82bd 100644
--- a/src/panfrost/bifrost/valhall/valhall.py
+++ b/src/panfrost/bifrost/valhall/valhall.py
@@ -344,6 +344,19 @@ for child in root.findall('enum'):
     enums[safe_name(child.attrib['name'])] = build_enum(child)
 
 MODIFIERS = {
+    # Texture instructions share a common encoding
+    "wide_indices": Flag("wide_indices", 8),
+    "array_enable": Flag("array_enable", 10),
+    "texel_offset": Flag("texel_offset", 11),
+    "shadow": Flag("shadow", 12),
+    "lod_mode": Modifier("lod_mode", 13, 3),
+    "write_mask": Modifier("write_mask", 22, 4),
+    "register_type": Modifier("register_type", 26, 2),
+    "dimension": Modifier("dimension", 28, 2),
+    "skip": Flag("skip", 39),
+    "register_width": Modifier("register_width", 46, 1, force_enum = "register_width"),
+    "secondary_register_width": Modifier("secondary_register_width", 47, 1, force_enum = "register_width"),
+
     "inactive_result": Modifier("inactive_result", 22, 4),
     "store_segment": Modifier("store_segment", 24, 2),
     "regfmt": Modifier("register_format", 24, 3),
@@ -359,6 +372,7 @@ MODIFIERS = {
     "cmp": Modifier("condition", 32, 3),
     "clamp": Modifier("clamp", 32, 2),
     "sr_count": Modifier("staging_register_count", 33, 3, implied = True),
+    "sr_write_count": Modifier("staging_register_write_count", 36, 3, implied = True),
 
     "conservative": Flag("conservative", 35),
     "subgroup": Modifier("subgroup_size", 36, 4),