Mesa (main): radv: Lower 8bit isub_sat/usub_sat.

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Module: Mesa
Branch: main
Commit: 55735ed728e130a57b2efb2232a178d7b998e3f7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=55735ed728e130a57b2efb2232a178d7b998e3f7

Author: Georg Lehmann <dadschoorse at gmail.com>
Date:   Sat Nov 20 14:33:20 2021 +0100

radv: Lower 8bit isub_sat/usub_sat.

Signed-off-by: Georg Lehmann <dadschoorse at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

---

 src/amd/vulkan/radv_pipeline.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5cf91b0a6e7..996a72a42ab 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4008,9 +4008,11 @@ lower_bit_size_callback(const nir_instr *instr, void *_)
       case nir_op_ushr:
       case nir_op_ishl:
       case nir_op_uadd_sat:
+      case nir_op_usub_sat:
          return (bit_size == 8 || !(chip >= GFX8 && nir_dest_is_divergent(alu->dest.dest))) ? 32
                                                                                             : 0;
       case nir_op_iadd_sat:
+      case nir_op_isub_sat:
          return bit_size == 8 || !nir_dest_is_divergent(alu->dest.dest) ? 32 : 0;
 
       default: