Mesa (main): radv, aco: Packed usub_sat/isub_sat.

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Module: Mesa
Branch: main
Commit: 1d815548ab957124d1c015fcde1e778f1e6a46dd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d815548ab957124d1c015fcde1e778f1e6a46dd

Author: Georg Lehmann <dadschoorse at gmail.com>
Date:   Thu Jan 20 20:50:15 2022 +0100

radv, aco: Packed usub_sat/isub_sat.

Signed-off-by: Georg Lehmann <dadschoorse at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13895>

---

 src/amd/compiler/aco_instruction_selection.cpp       | 10 ++++++++++
 src/amd/compiler/aco_instruction_selection_setup.cpp |  2 ++
 src/amd/vulkan/radv_pipeline.c                       |  2 ++
 3 files changed, 14 insertions(+)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index a335c0f9a5c..a81b24bd5ba 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2102,6 +2102,11 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
       break;
    }
    case nir_op_usub_sat: {
+      if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+         Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst);
+         sub_instr->vop3p().clamp = 1;
+         break;
+      }
       Temp src0 = get_alu_src(ctx, instr->src[0]);
       Temp src1 = get_alu_src(ctx, instr->src[1]);
       if (dst.regClass() == s1) {
@@ -2179,6 +2184,11 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
       break;
    }
    case nir_op_isub_sat: {
+      if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
+         Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_i16, dst);
+         sub_instr->vop3p().clamp = 1;
+         break;
+      }
       Temp src0 = get_alu_src(ctx, instr->src[0]);
       Temp src1 = get_alu_src(ctx, instr->src[1]);
       if (dst.regClass() == s1) {
diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 63325634379..04d664999d4 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -560,6 +560,8 @@ init_context(isel_context* ctx, nir_shader* shader)
                case nir_op_iadd_sat:
                case nir_op_uadd_sat:
                case nir_op_isub:
+               case nir_op_isub_sat:
+               case nir_op_usub_sat:
                case nir_op_imul:
                case nir_op_imin:
                case nir_op_imax:
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 996a72a42ab..2a6f54bc45e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4068,6 +4068,8 @@ opt_vectorize_callback(const nir_instr *instr, const void *_)
    case nir_op_iadd_sat:
    case nir_op_uadd_sat:
    case nir_op_isub:
+   case nir_op_isub_sat:
+   case nir_op_usub_sat:
    case nir_op_imul:
    case nir_op_imin:
    case nir_op_imax: