Mesa (main): anv, iris: Enable compute engine with INTEL_COMPUTE_CLASS=1

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 81d6ae31d6f18d6fd2894a8b6dfe4323eea797f9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=81d6ae31d6f18d6fd2894a8b6dfe4323eea797f9

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Wed Nov 17 12:08:25 2021 -0800

anv, iris: Enable compute engine with INTEL_COMPUTE_CLASS=1

If this environment variable is set, then a detected compute engine
will be used as described in docs/envvars.rst.

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira at intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395>

---

 docs/envvars.rst                      | 6 ++++++
 src/gallium/drivers/iris/iris_batch.c | 3 ++-
 src/intel/vulkan/anv_device.c         | 2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/docs/envvars.rst b/docs/envvars.rst
index 1503651ff93..027952f1b3d 100644
--- a/docs/envvars.rst
+++ b/docs/envvars.rst
@@ -246,6 +246,12 @@ Intel driver environment variables
    if set to 1, true or yes, then the OpenGL implementation will
    default ``GL_BLACKHOLE_RENDER_INTEL`` to true, thus disabling any
    rendering.
+:envvar:`INTEL_COMPUTE_CLASS`
+   If set to 1, true or yes, then I915_ENGINE_CLASS_COMPUTE will be
+   supported. For OpenGL, iris will attempt to use a compute engine
+   for compute dispatches if one is detected. For Vulkan, anvil will
+   advertise support for a compute queue if a compute engine is
+   detected.
 :envvar:`INTEL_DEBUG`
    a comma-separated list of named flags, which do various things:
 
diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index 15eb5229af5..9886497ca25 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -49,6 +49,7 @@
 #include "intel/common/intel_gem.h"
 #include "intel/ds/intel_tracepoints.h"
 #include "util/hash_table.h"
+#include "util/debug.h"
 #include "util/set.h"
 #include "util/u_upload_mgr.h"
 
@@ -291,7 +292,7 @@ iris_create_engines_context(struct iris_context *ice, int priority)
    /* Blitter is only supported on Gfx12+ */
    unsigned num_batches = IRIS_BATCH_COUNT - (devinfo->ver >= 12 ? 0 : 1);
 
-   if (false /* Disable for now. We will enable with an env-var. */ &&
+   if (env_var_as_boolean("INTEL_COMPUTE_CLASS", false) &&
        intel_gem_count_engines(engines_info, I915_ENGINE_CLASS_COMPUTE) > 0)
       engine_classes[IRIS_BATCH_COMPUTE] = I915_ENGINE_CLASS_COMPUTE;
 
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 2e3255bbec2..349d14e602d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -701,7 +701,7 @@ anv_physical_device_init_queue_families(struct anv_physical_device *pdevice)
                                  I915_ENGINE_CLASS_RENDER);
       int g_count = 0;
       int c_count = 0;
-      if (false /* Disable for now. We will enable with an env-var. */)
+      if (env_var_as_boolean("INTEL_COMPUTE_CLASS", false))
          c_count = intel_gem_count_engines(pdevice->engine_info,
                                            I915_ENGINE_CLASS_COMPUTE);
       enum drm_i915_gem_engine_class compute_class =