Mesa (main): tu: Fix 3d GMEM store swizzle in texture descriptor

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 705c0d0373b5ff7963eb54e944620c4991c3ecdf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=705c0d0373b5ff7963eb54e944620c4991c3ecdf

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Wed Jun 15 16:27:49 2022 +0200

tu: Fix 3d GMEM store swizzle in texture descriptor

Even though image views for attachments must use the identity swizzle,
there are cases where we have to add in our own swizzle, in particular
for D24S8 when the view is depth-only/stencil-only. Therefore we have to
reset it to the identity, similar to what we do with input attachments.

Fixes: b157a5d ("tu: Implement non-aligned multisample GMEM STORE_OP_STORE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17058>

---

 src/freedreno/ci/freedreno-a630-fails.txt | 23 -----------------------
 src/freedreno/vulkan/tu_clear_blit.c      | 12 +++++++++---
 2 files changed, 9 insertions(+), 26 deletions(-)

diff --git a/src/freedreno/ci/freedreno-a630-fails.txt b/src/freedreno/ci/freedreno-a630-fails.txt
index 88d3a6a521b..ac87377170f 100644
--- a/src/freedreno/ci/freedreno-a630-fails.txt
+++ b/src/freedreno/ci/freedreno-a630-fails.txt
@@ -607,29 +607,6 @@ spec@!opengl 3.2 at gl-3.2-adj-prims line cull-back pv-first,Fail
 spec@!opengl 3.2 at gl-3.2-adj-prims line cull-front pv-first,Fail
 spec@!opengl 3.2 at gl-3.2-adj-prims pv-first,Fail
 
-# Failures with unaligned gmem store
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_2.d24_unorm_s8_uint_separate_layouts.compatibility_depth_zero_stencil_zero_testing_stencil,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_32_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_8_32.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_49_13.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_5_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_2.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
-gmem-unaligned-dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_17_1.samples_4.d24_unorm_s8_uint_separate_layouts.depth_zero_stencil_zero_testing_stencil_samplemask,Fail
 spec@!opengl 1.0 at depth-clear-precision-check,Fail
 spec@!opengl 1.0 at depth-clear-precision-check@depth24,Fail
 spec@!opengl 1.0 at depth-clear-precision-check@depth24_stencil8,Fail
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c
index 645b34dc779..375b8f93e23 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -945,9 +945,15 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd,
    uint32_t desc[A6XX_TEX_CONST_DWORDS];
    memcpy(desc, iview->view.descriptor, sizeof(desc));
 
-   /* patch the format so that depth/stencil get the right format */
-   desc[0] &= ~A6XX_TEX_CONST_0_FMT__MASK;
-   desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt);
+   /* patch the format so that depth/stencil get the right format and swizzle */
+   desc[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK |
+                A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK |
+                A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK);
+   desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt) |
+               A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_X) |
+               A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_Y) |
+               A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_Z) |
+               A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_W);
 
    /* patched for gmem */
    desc[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);