Mesa (main): radeonsi/gfx11: set BIG_PAGE for the attribute ring

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3382af7f6a7508d2f1f698a39f9761a88c5e863a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3382af7f6a7508d2f1f698a39f9761a88c5e863a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun May 15 01:43:01 2022 -0400

radeonsi/gfx11: set BIG_PAGE for the attribute ring

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>

---

 src/amd/common/ac_gpu_info.c             | 9 +++++++++
 src/amd/common/ac_gpu_info.h             | 1 +
 src/gallium/drivers/radeonsi/si_buffer.c | 5 ++++-
 src/gallium/drivers/radeonsi/si_state.c  | 1 +
 4 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 16e9ec82a62..ca7e4aab479 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -1222,6 +1222,13 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256;
    info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4;
 
+   /* BIG_PAGE is supported since gfx10.3 and requires VRAM. VRAM is only guaranteed
+    * with AMDGPU_GEM_CREATE_DISCARDABLE. DISCARDABLE was added in DRM 3.47.0.
+    */
+   info->discardable_allows_big_page = info->gfx_level >= GFX10_3 &&
+                                       info->has_dedicated_vram &&
+                                       info->drm_minor >= 47;
+
    /* The maximum number of scratch waves. The number is only a function of the number of CUs.
     * It should be large enough to hold at least 1 threadgroup. Use the minimum per-SA CU count.
     *
@@ -1342,6 +1349,8 @@ void ac_print_gpu_info(struct radeon_info *info, FILE *f)
    fprintf(f, "    never_stop_sq_perf_counters = %i\n", info->never_stop_sq_perf_counters);
    fprintf(f, "    has_sqtt_rb_harvest_bug = %i\n", info->has_sqtt_rb_harvest_bug);
    fprintf(f, "    has_sqtt_auto_flush_mode_bug = %i\n", info->has_sqtt_auto_flush_mode_bug);
+   fprintf(f, "    never_send_perfcounter_stop = %i\n", info->never_send_perfcounter_stop);
+   fprintf(f, "    discardable_allows_big_page = %i\n", info->discardable_allows_big_page);
 
    fprintf(f, "Display features:\n");
    fprintf(f, "    use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 1bd245b1acf..07f1cbb556f 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -97,6 +97,7 @@ struct radeon_info {
    bool has_sqtt_rb_harvest_bug;
    bool has_sqtt_auto_flush_mode_bug;
    bool never_send_perfcounter_stop;
+   bool discardable_allows_big_page;
 
    /* Display features. */
    /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index ce60e94c131..b468a297646 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -148,8 +148,11 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
       res->flags |= RADEON_FLAG_GL2_BYPASS;
 
    if (res->b.b.flags & SI_RESOURCE_FLAG_DISCARDABLE &&
-       sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 47)
+       sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 47) {
+      /* Assume VRAM, so that we can use BIG_PAGE. */
+      assert(res->domains == RADEON_DOMAIN_VRAM);
       res->flags |= RADEON_FLAG_DISCARDABLE;
+   }
 
    if (res->domains == RADEON_DOMAIN_VRAM &&
        sscreen->options.mall_noalloc)
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 69d3cd859b2..53dd6fcca02 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -5913,6 +5913,7 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
       si_pm4_set_reg(pm4, R_03111C_SPI_ATTRIBUTE_RING_SIZE,
                      S_03111C_MEM_SIZE(((sscreen->attribute_ring->bo_size /
                                          sscreen->info.max_se) >> 16) - 1) |
+                     S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |
                      S_03111C_L1_POLICY(1));
    }