[Mesa-dev] [PATCH 1/2] i965/fs: Add gen6 register spilling support.

[Zou, Nanhai]

I think that probably  not single thread. 
But Bspec says to recalculate max vs and wm thread if using scratch to avoid use out scrach space and to avoid deadlock.
I don't know what the deadlock means there.

Thanks
Zou Nanhai

>>-----Original Message-----
>>From: mesa-dev-bounces+nanhai.zou=intel.com at lists.freedesktop.org
>>[mailto:mesa-dev-bounces+nanhai.zou=intel.com at lists.freedesktop.org] On
>>Behalf Of Kenneth Graunke
>>Sent: 2011年4月15日 15:09
>>To: mesa-dev at lists.freedesktop.org
>>Subject: Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add gen6 register spilling
>>support.
>>
>>On 04/15/2011 12:00 AM, Zou, Nanhai wrote:
>>> Hi Eric,
>>> 	BSpec says VS and WM should fall to single thread to avoid racing if use
>>scratch space.
>>>
>>> Thanks
>>> Zou Nanhai
>>
>>Hrm.  Do you have a volume/section reference?  I thought that scratch
>>space was done (or could be done) on a per-thread basis.
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