[Mesa-dev] [PATCH] r600g: Add support for ROUND, v2

[Roland Scheidegger]

This looks like the right approach to me.
Note that RNDNE is in fact the default rounding mode for IEEE_754-2008
(in fact it was the default for earlier ieee-754 too).
So I see no reason to deviate from that unless there would be some very
good reason, even if it may look "wrong" for humans.

Roland

Am 08.08.2011 11:32, schrieb Lauri Kasanen:
> From f76d23a57996eea6862d3bd899e08f9cb3ac5dec Mon Sep 17 00:00:00 2001
> From: Lauri Kasanen <cand at gmx.com>
> Date: Mon, 8 Aug 2011 12:20:27 +0300
> Subject: [PATCH] r600g: Add support for ROUND, v2
> 
> This is a GLSL 1.3 feature, but also used by MLAA.
> 
> Signed-off-by: Lauri Kasanen <cand at gmx.com>
> ---
>  src/gallium/drivers/r600/r600_asm.c    |    2 ++
>  src/gallium/drivers/r600/r600_shader.c |    6 +++---
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c
> index 5fae2b0..24af991 100644
> --- a/src/gallium/drivers/r600/r600_asm.c
> +++ b/src/gallium/drivers/r600/r600_asm.c
> @@ -88,6 +88,7 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
>  		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
>  		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
>  		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
> +		case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
>  			return 1;
>  		default: R600_ERR(
>  			"Need instruction operand number for 0x%x.\n", alu->inst);
> @@ -140,6 +141,7 @@ static inline unsigned int r600_bc_get_num_operands(struct r600_bc *bc, struct r
>  		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT:
>  		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_SIN:
>  		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_COS:
> +		case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE:
>  			return 1;
>  		default: R600_ERR(
>  			"Need instruction operand number for 0x%x.\n", alu->inst);
> diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
> index 3e21ad1..4034a93 100644
> --- a/src/gallium/drivers/r600/r600_shader.c
> +++ b/src/gallium/drivers/r600/r600_shader.c
> @@ -3228,7 +3228,7 @@ static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
>  	{TGSI_OPCODE_FRC,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
>  	{TGSI_OPCODE_CLAMP,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
>  	{TGSI_OPCODE_FLR,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
> -	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
> +	{TGSI_OPCODE_ROUND,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
>  	{TGSI_OPCODE_EX2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
>  	{TGSI_OPCODE_LG2,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
>  	{TGSI_OPCODE_POW,	0, V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
> @@ -3386,7 +3386,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = {
>  	{TGSI_OPCODE_FRC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
>  	{TGSI_OPCODE_CLAMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
>  	{TGSI_OPCODE_FLR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
> -	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
> +	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
>  	{TGSI_OPCODE_EX2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, tgsi_trans_srcx_replicate},
>  	{TGSI_OPCODE_LG2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, tgsi_trans_srcx_replicate},
>  	{TGSI_OPCODE_POW,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_pow},
> @@ -3544,7 +3544,7 @@ static struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] = {
>  	{TGSI_OPCODE_FRC,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT, tgsi_op2},
>  	{TGSI_OPCODE_CLAMP,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
>  	{TGSI_OPCODE_FLR,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FLOOR, tgsi_op2},
> -	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported},
> +	{TGSI_OPCODE_ROUND,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_RNDNE, tgsi_op2},
>  	{TGSI_OPCODE_EX2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_EXP_IEEE, cayman_emit_float_instr},
>  	{TGSI_OPCODE_LG2,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_LOG_IEEE, cayman_emit_float_instr},
>  	{TGSI_OPCODE_POW,	0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, cayman_pow},