[Mesa-dev] [PATCH 5/5] i965: increase the brw eu instruction store size dynamically

[Yuanhan Liu]

Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 10000'.

Signed-off-by: Yuanhan Liu <yuanhan.liu at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_eu.c      |    7 +++++++
 src/mesa/drivers/dri/i965/brw_eu.h      |    7 ++++---
 src/mesa/drivers/dri/i965/brw_eu_emit.c |   22 +++++++++++++++++++---
 3 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 77eb2cf..f13affe 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -174,6 +174,13 @@ void
 brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
 {
    p->brw = brw;
+   /*
+    * Set the initial instruction store array size to 1024, if found that
+    * isn't enough, then it will double the store size at brw_next_insn()
+    * until it meet the BRW_EU_MAX_INSN
+    */
+   p->store_size = 1024;
+   p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
    p->nr_insn = 0;
    p->current = p->stack;
    p->compressed = false;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 18dd9c7..e86efe6 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -100,11 +100,12 @@ struct brw_glsl_call;
 
 
 
-#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 10000
+#define BRW_EU_MAX_INSN_STACK   5
+#define BRW_EU_MAX_INSN         (1024 * 1024)
 
 struct brw_compile {
-   struct brw_instruction store[BRW_EU_MAX_INSN];
+   struct brw_instruction *store;
+   int store_size;
    GLuint nr_insn;
 
    void *mem_ctx;
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 29dd623..25f2feb 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -688,7 +688,17 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
 {
    struct brw_instruction *insn;
 
-   assert(p->nr_insn + 1 < BRW_EU_MAX_INSN);
+   if (p->nr_insn + 1 > p->store_size) {
+      if (p->nr_insn + 1 > BRW_EU_MAX_INSN) {
+         assert(!"exceed max brw allowed eu instructions");
+      } else {
+         if (0)
+            printf("incresing the store size to %d\n", p->store_size << 1);
+         p->store_size <<= 1;
+         p->store = reralloc(p->mem_ctx, p->store,
+                             struct brw_instruction, p->store_size);
+      }
+   }
 
    insn = &p->store[p->nr_insn++];
    memcpy(insn, p->current, sizeof(*insn));
@@ -1150,6 +1160,14 @@ brw_ENDIF(struct brw_compile *p)
    struct brw_instruction *else_inst = NULL;
    struct brw_instruction *if_inst = NULL;
 
+   /*
+    * next_insn() may change the base address of instruction store
+    * memory(p->store), so call it first before referencing the
+    * instruction store pointer from an index.
+    */
+   if (!p->single_program_flow)
+      insn = next_insn(p, BRW_OPCODE_ENDIF);
+
    /* Pop the IF and (optional) ELSE instructions from the stack */
    p->if_stack_depth--;
    if (p->store[p->if_stack[p->if_stack_depth]].header.opcode == BRW_OPCODE_ELSE) {
@@ -1164,8 +1182,6 @@ brw_ENDIF(struct brw_compile *p)
       return;
    }
 
-   insn = next_insn(p, BRW_OPCODE_ENDIF);
-
    if (intel->gen < 6) {
       brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
       brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
-- 
1.7.4.4