[Mesa-dev] [PATCH 2/8] intel: Move S8 width/height alignment to miptree creation.
Eric Anholt
eric at anholt.net
Thu Dec 8 13:39:57 PST 2011
We were doing it in the caller in the renderbuffer code, but it was
missed in the separate stencil creation for textures. Apparently our
testing was using renderbuffers or pre-aligned sizes.
---
src/mesa/drivers/dri/intel/intel_fbo.c | 44 +----------------------
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 31 +++++++++++------
src/mesa/drivers/dri/intel/intel_mipmap_tree.h | 2 -
3 files changed, 22 insertions(+), 55 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
index 1980355..ebd218f 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -193,7 +193,7 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
{
struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- int cpp, tiling;
+ int cpp;
ASSERT(rb->Name != 0);
@@ -226,7 +226,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
rb->Height = height;
rb->_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
rb->DataType = intel_mesa_format_to_rb_datatype(rb->Format);
- cpp = _mesa_get_format_bytes(rb->Format);
intel_flush(ctx);
@@ -236,45 +235,7 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
_mesa_lookup_enum_by_nr(internalFormat),
_mesa_get_format_name(rb->Format), width, height);
- tiling = I915_TILING_NONE;
- if (intel->use_texture_tiling) {
- GLenum base_format = _mesa_get_format_base_format(rb->Format);
-
- if (intel->gen >= 4 && (base_format == GL_DEPTH_COMPONENT ||
- base_format == GL_STENCIL_INDEX ||
- base_format == GL_DEPTH_STENCIL))
- tiling = I915_TILING_Y;
- else
- tiling = I915_TILING_X;
- }
-
- if (irb->Base.Format == MESA_FORMAT_S8) {
- /*
- * The stencil buffer is W tiled. However, we request from the kernel a
- * non-tiled buffer because the GTT is incapable of W fencing.
- *
- * The stencil buffer has quirky pitch requirements. From Vol 2a,
- * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
- * The pitch must be set to 2x the value computed based on width, as
- * the stencil buffer is stored with two rows interleaved.
- * To accomplish this, we resort to the nasty hack of doubling the drm
- * region's cpp and halving its height.
- *
- * If we neglect to double the pitch, then render corruption occurs.
- */
- irb->mt = intel_miptree_create_for_renderbuffer(
- intel,
- rb->Format,
- I915_TILING_NONE,
- cpp * 2,
- ALIGN(width, 64),
- ALIGN((height + 1) / 2, 64));
- if (!irb->mt)
- return false;
-
- } else if (irb->Base.Format == MESA_FORMAT_S8_Z24
- && intel->has_separate_stencil) {
-
+ if (irb->Base.Format == MESA_FORMAT_S8_Z24 && intel->has_separate_stencil) {
bool ok = true;
struct gl_renderbuffer *depth_rb;
struct gl_renderbuffer *stencil_rb;
@@ -315,7 +276,6 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct gl_renderbuffer
} else {
irb->mt = intel_miptree_create_for_renderbuffer(intel, rb->Format,
- tiling, cpp,
width, height);
if (!irb->mt)
return false;
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 160e5cc..989038e 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -162,12 +162,28 @@ intel_miptree_create(struct intel_context *intel,
(base_format == GL_DEPTH_COMPONENT ||
base_format == GL_DEPTH_STENCIL_EXT))
tiling = I915_TILING_Y;
- else if (format == MESA_FORMAT_S8)
- tiling = I915_TILING_NONE;
else if (width0 >= 64)
tiling = I915_TILING_X;
}
+ if (format == MESA_FORMAT_S8) {
+ /* The stencil buffer is W tiled. However, we request from the kernel a
+ * non-tiled buffer because the GTT is incapable of W fencing.
+ *
+ * The stencil buffer has quirky pitch requirements. From Vol 2a,
+ * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
+ * The pitch must be set to 2x the value computed based on width, as
+ * the stencil buffer is stored with two rows interleaved.
+ * To accomplish this, we resort to the nasty hack of doubling the drm
+ * region's cpp and halving its height.
+ *
+ * If we neglect to double the pitch, then render corruption occurs.
+ */
+ tiling = I915_TILING_NONE;
+ width0 = ALIGN(width0, 64);
+ height0 = ALIGN((height0 + 1) / 2, 64);
+ }
+
mt = intel_miptree_create_internal(intel, target, format,
first_level, last_level, width0,
height0, depth0);
@@ -217,21 +233,14 @@ intel_miptree_create_for_region(struct intel_context *intel,
struct intel_mipmap_tree*
intel_miptree_create_for_renderbuffer(struct intel_context *intel,
gl_format format,
- uint32_t tiling,
- uint32_t cpp,
uint32_t width,
uint32_t height)
{
- struct intel_region *region;
struct intel_mipmap_tree *mt;
- region = intel_region_alloc(intel->intelScreen,
- tiling, cpp, width, height, true);
- if (!region)
- return NULL;
+ mt = intel_miptree_create(intel, GL_TEXTURE_2D, format, 0, 0,
+ width, height, 1, true);
- mt = intel_miptree_create_for_region(intel, GL_TEXTURE_2D, format, region);
- intel_region_release(®ion);
return mt;
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 24c00ac..c24fa8e 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -246,8 +246,6 @@ intel_miptree_create_for_region(struct intel_context *intel,
struct intel_mipmap_tree*
intel_miptree_create_for_renderbuffer(struct intel_context *intel,
gl_format format,
- uint32_t tiling,
- uint32_t cpp,
uint32_t width,
uint32_t height);
--
1.7.7.3
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