[Mesa-dev] [PATCH 1/3 v2] i965: Check actual tile offsets in Gen4 miptree workaround.

[Chad Versace]

On 07/25/2011 05:06 PM, Kenneth Graunke wrote:
> The apitrace dump in bug #34009 managed to fool the draw_offset check
> into thinking that we were tile aligned when we weren't.  This led to an
> assertion failure in brw_update_renderbuffer_surface with tile_y != 0.
> 
> Simply compute tile_x and tile_y and check those, as that way both
> places are checking the same thing.
> 
> NOTE: This is a candidate for stable release branches.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34009
> Cc: Chad Versace <chad at chad-versace.us>
> Cc: Eric Anholt <eric at anholt.net>
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> ---
>  src/mesa/drivers/dri/intel/intel_fbo.c |   28 ++++++++++++++++++++++++++--
>  1 files changed, 26 insertions(+), 2 deletions(-)
> 
> v2 doesn't break the faked packed/depth stencil on Ivybridge (there is no
> irb->region on the wrapper), and introduces a function (since I need to add
> more conditions in a third patch.)
> 
> diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c
> index 35be325..90bfe96 100644
> --- a/src/mesa/drivers/dri/intel/intel_fbo.c
> +++ b/src/mesa/drivers/dri/intel/intel_fbo.c
> @@ -647,6 +647,22 @@ intel_renderbuffer_tile_offsets(struct intel_renderbuffer *irb,
>     }
>  }
>  
> +#ifndef I915
> +static bool
> +need_tile_offset_workaround(struct brw_context *brw,
> +			    struct intel_renderbuffer *irb)
> +{
> +   uint32_t tile_x, tile_y;
> +
> +   intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
> +
> +   if (!brw->has_surface_tile_offset)
> +      return tile_x != 0 || tile_y != 0;
> +
> +   return false;
> +}
> +#endif
> +
>  /**
>   * Called by glFramebufferTexture[123]DEXT() (and other places) to
>   * prepare for rendering into texture memory.  This might be called
> @@ -699,9 +715,17 @@ intel_render_texture(struct gl_context * ctx,
>     intel_renderbuffer_set_draw_offset(irb, intel_image, att->Zoffset);
>     intel_image->used_as_render_target = GL_TRUE;
>  
> +   bool is_depthbuffer = irb->Base._BaseFormat == GL_DEPTH_COMPONENT ||
> +			 irb->Base._BaseFormat == GL_DEPTH_STENCIL;
> +
> +   /* Resolve combined depth/stencil wrapper to get at the real depth buffer.
> +    * Notably, we don't need the original irb after this point.
> +    */
> +   if (is_depthbuffer)
> +      irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
> +
>  #ifndef I915
> -   if (!brw_context(ctx)->has_surface_tile_offset &&
> -       (irb->draw_offset & 4095) != 0) {

Why did you remove `(irb->draw_offset & 4095) != 0`? It's not evident from the patch.

> +   if (need_tile_offset_workaround(brw_context(ctx), irb)) {
>        /* Original gen4 hardware couldn't draw to a non-tile-aligned
>         * destination in a miptree unless you actually setup your
>         * renderbuffer as a miptree and used the fragile


-- 
Chad Versace
chad at chad-versace.us

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