[Mesa-dev] [PATCH 1/2] i965/brw: Emit state for hiz and separate stencil buffers

[Chad Versace]

On Sun, 05 Jun 2011 01:37:27 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
> On 06/04/2011 04:29 PM, Chad Versace wrote:
> > On 06/03/2011 03:33 PM, Kenneth Graunke wrote:
> >> Do we need to emit 3DSTATE_STENCIL_BUFFER with all 0's in the stencil_irb == NULL case?  Ditto for HiZ I guess.  Just being a
> >> bit paranoid.
> >
> > The test results for these paranoiac cases pass, so paranoia is unneeded. Regarding "Do we need to emit 3DSTATE_STENCIL_BUFFER
> > with all 0's in the stencil_irb == NULL case", see tests:
> > 	* hiz-depth-test-fbo-d24-s0 : column 6
> > 	* hiz-depth-stencil-fbo-d24-s0 : columns 3, 6
> > Regarding "Ditto for HiZ", the following test runs emit a stencil buffer but no hiz buffer:
> > 	* hiz-stencil-test-fbo-d0-s8 : column 6
> > 	* hiz-stencil-read-fbo-d0-s8 : column 6
> > 	* hiz-depth-stencil-fbo-d0-s8 : column 6
> 
> Hrm.  I was thinking of a slightly more elaborate case: Render to an FBO 
> that has both depth and stencil...then render to another FBO that only 
> has depth.  The question is: would the old stencil buffer stay 
> programmed and somehow get used.  Although come to think of it, I think 
> the "Separate Stencil Enable" bit in 3DSTATE_DEPTH_BUFFER ought to be 
> sufficient.  So it's probably okay.

To be extra safe, we could upload a zero-ish 3DSTATE_STENCIL_BUFFER when there
is no stencil buffer. But, that upload is really wasted bandwidth, since the
separate-stencil-enable bit is disabled and hardware won't read
3DSTATE_STENCIL_BUFFER anyway.