[Mesa-dev] [PATCH 3/3] intel: Add support copying Y-tiled buffers with the Gen6 blitter.

[Kenneth Graunke]

According to the Sandybridge PRM, Volume 1, Part 5, Section 1.9.15,
Gen6's blitter supports Y-tiled buffers as well as X-tiled.  Pitch is
specified in 512-byte granularity for X-tiled, but 128-byte for Y-tiled.

Gen5 and earlier unfortunately only support X-tiled buffers.

Fixes a software fallback in PlaneShift 0.5.7 when casting spells.

NOTE: This is a candidate for the 7.10 and 7.11 branches.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/intel/intel_blit.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c
index 30be1b9..de752f2 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -111,13 +111,13 @@ intelEmitCopyBlit(struct intel_context *intel,
    if (dst_tiling != I915_TILING_NONE) {
       if (dst_offset & 4095)
 	 return GL_FALSE;
-      if (dst_tiling == I915_TILING_Y)
+      if (intel->gen < 6 && dst_tiling == I915_TILING_Y)
 	 return GL_FALSE;
    }
    if (src_tiling != I915_TILING_NONE) {
       if (src_offset & 4095)
 	 return GL_FALSE;
-      if (src_tiling == I915_TILING_Y)
+      if (intel->gen < 6 && src_tiling == I915_TILING_Y)
 	 return GL_FALSE;
    }
 
@@ -172,13 +172,15 @@ intelEmitCopyBlit(struct intel_context *intel,
    }
 
 #ifndef I915
-   if (dst_tiling != I915_TILING_NONE) {
+   if (dst_tiling == I915_TILING_NONE) {
       CMD |= XY_DST_TILED;
-      dst_pitch /= 4;
+      if (dst_tiling == I915_TILING_X)
+	 dst_pitch /= 4;
    }
    if (src_tiling != I915_TILING_NONE) {
       CMD |= XY_SRC_TILED;
-      src_pitch /= 4;
+      if (src_tiling == I915_TILING_X)
+	 src_pitch /= 4;
    }
 #endif
 
-- 
1.7.6