[Mesa-dev] [PATCH 11/14] i965: Emit 3D_STATE_HIER_DEPTH_BUFFER

[chad at chad-versace.us]

From: Chad Versace <chad.versace at intel.com>

... when a HiZ region is present. Also change the hiz bits and depth
format in 3D_STATE_DEPTH_BUFFER.

Signed-off-by: Chad Versace <chad.versace at intel.com>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c |   47 +++++++++++++++++++++++++---
 1 files changed, 42 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 8d1832d..874a1d5 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -32,6 +32,7 @@
 
 
 #include "intel_batchbuffer.h"
+#include "intel_fbo.h"
 #include "intel_regions.h"
 
 #include "brw_context.h"
@@ -188,15 +189,21 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
 static void prepare_depthbuffer(struct brw_context *brw)
 {
    struct intel_region *depth_region = brw->state.depth_region;
+   struct intel_region *hiz_region =
+      intel_framebuffer_get_hiz_region(brw->intel.ctx.DrawBuffer);
 
    if (depth_region != NULL)
       brw_add_validated_bo(brw, depth_region->buffer);
+   if (hiz_region != NULL)
+      brw_add_validated_bo(brw, hiz_region->buffer);
 }
 
 static void emit_depthbuffer(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
    struct intel_region *depth_region = brw->state.depth_region;
+   struct intel_region *hiz_region =
+         intel_framebuffer_get_hiz_region(intel->ctx.DrawBuffer);
    unsigned int len;
 
    if (intel->gen >= 6)
@@ -232,8 +239,12 @@ static void emit_depthbuffer(struct brw_context *brw)
       case 4:
 	 if (intel->depth_buffer_is_float)
 	    format = BRW_DEPTHFORMAT_D32_FLOAT;
-	 else
-	    format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
+	 else {
+	    if (hiz_region)
+	       format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT;
+	    else
+	       format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
+	 }
 	 break;
       default:
 	 assert(0);
@@ -241,11 +252,18 @@ static void emit_depthbuffer(struct brw_context *brw)
       }
 
       assert(depth_region->tiling != I915_TILING_X);
-      assert(intel->gen < 6 || depth_region->tiling == I915_TILING_Y);
+      /*
+       * If HiZ is enabled on Gen5, then Y tiling must be used. See Vol 2,
+       * Section 11.5.6.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 "Tiled Surface".
+       */
+      assert((intel->gen < 6 && !hiz_region)
+             || depth_region->tiling == I915_TILING_Y);
 
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
       OUT_BATCH(((depth_region->pitch * depth_region->cpp) - 1) |
+		((hiz_region ? 1 : 0) << 21) | /* hiearchical depth buffer enable */
+		((hiz_region ? 1 : 0) << 22) | /* separate stencil buffer enable */
 		(format << 18) |
 		(BRW_TILEWALK_YMAJOR << 26) |
 		((depth_region->tiling != I915_TILING_NONE) << 27) |
@@ -267,8 +285,27 @@ static void emit_depthbuffer(struct brw_context *brw)
       ADVANCE_BATCH();
    }
 
-   /* Initialize it for safety. */
-   if (intel->gen >= 6) {
+   /* Emit batch for HiZ buffer. */
+   if (hiz_region) {
+      BEGIN_BATCH(3);
+      OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
+      OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
+      OUT_RELOC(hiz_region->buffer,
+                I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+                0);
+      ADVANCE_BATCH();
+   }
+
+   /*
+    * Emit clear params for safety.
+    *
+    * If hiz is enabled, then clear params must be emitted. From Vol 2,
+    * Section 11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
+    *   [DevIL], [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the
+    *   DEPTH_BUFFER_STATE packet when HiZ is enabled and the DEPTH_BUFFER_STATE
+    *   changes.
+    */
+   if (intel->gen >= 6 || hiz_region) {
       BEGIN_BATCH(2);
       OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2));
       OUT_BATCH(0);
-- 
1.7.5