[Mesa-dev] [PATCH 10/14] i965: Refactor prepare_depthbuffer() and emit_depthbuffer()

[chad at chad-versace.us]

From: Chad Versace <chad.versace at intel.com>

Rename variable 'region' to 'depth_region'. This removes naming ambiguity
introduced by the next commit, which introduces the variable 'hiz_region'.

Signed-off-by: Chad Versace <chad.versace at intel.com>
---
 src/mesa/drivers/dri/i965/brw_misc_state.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 7119786..8d1832d 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -187,16 +187,16 @@ const struct brw_tracked_state brw_psp_urb_cbs = {
 
 static void prepare_depthbuffer(struct brw_context *brw)
 {
-   struct intel_region *region = brw->state.depth_region;
+   struct intel_region *depth_region = brw->state.depth_region;
 
-   if (region != NULL)
-      brw_add_validated_bo(brw, region->buffer);
+   if (depth_region != NULL)
+      brw_add_validated_bo(brw, depth_region->buffer);
 }
 
 static void emit_depthbuffer(struct brw_context *brw)
 {
    struct intel_context *intel = &brw->intel;
-   struct intel_region *region = brw->state.depth_region;
+   struct intel_region *depth_region = brw->state.depth_region;
    unsigned int len;
 
    if (intel->gen >= 6)
@@ -206,7 +206,7 @@ static void emit_depthbuffer(struct brw_context *brw)
    else
       len = 5;
 
-   if (region == NULL) {
+   if (depth_region == NULL) {
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
@@ -225,7 +225,7 @@ static void emit_depthbuffer(struct brw_context *brw)
    } else {
       unsigned int format;
 
-      switch (region->cpp) {
+      switch (depth_region->cpp) {
       case 2:
 	 format = BRW_DEPTHFORMAT_D16_UNORM;
 	 break;
@@ -240,22 +240,22 @@ static void emit_depthbuffer(struct brw_context *brw)
 	 return;
       }
 
-      assert(region->tiling != I915_TILING_X);
-      assert(intel->gen < 6 || region->tiling == I915_TILING_Y);
+      assert(depth_region->tiling != I915_TILING_X);
+      assert(intel->gen < 6 || depth_region->tiling == I915_TILING_Y);
 
       BEGIN_BATCH(len);
       OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
-      OUT_BATCH(((region->pitch * region->cpp) - 1) |
+      OUT_BATCH(((depth_region->pitch * depth_region->cpp) - 1) |
 		(format << 18) |
 		(BRW_TILEWALK_YMAJOR << 26) |
-		((region->tiling != I915_TILING_NONE) << 27) |
+		((depth_region->tiling != I915_TILING_NONE) << 27) |
 		(BRW_SURFACE_2D << 29));
-      OUT_RELOC(region->buffer,
+      OUT_RELOC(depth_region->buffer,
 		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 		0);
       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
-		((region->width - 1) << 6) |
-		((region->height - 1) << 19));
+		((depth_region->width - 1) << 6) |
+		((depth_region->height - 1) << 19));
       OUT_BATCH(0);
 
       if (intel->is_g4x || intel->gen >= 5)
-- 
1.7.5