[Mesa-dev] [PATCH] r600g: lazy load for AR register

[Kai Wasserbäch]

Vadim Girlin <vadimgirlin <at> gmail.com> writes:

> diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
> index c4cc922..7414c73 100644
> --- a/src/gallium/drivers/r600/r600_asm.c
> +++ b/src/gallium/drivers/r600/r600_asm.c
> 
> [...]
> 
> @@ -1201,6 +1202,36 @@ static int r600_bytecode_alloc_kcache_lines(struct
r600_bytecode *bc, struct r60
>  	return 0;
>  }
> 
> +/* load AR register from gpr (bc->ar_reg) with MOVA_INT */
> +static int load_ar(struct r600_bytecode *bc)
> +{
> +	struct r600_bytecode_alu alu;
> +	int r;
> +
> +	if (bc->ar_loaded)
> +		return 0;
> +
> +	/* hack to avoid making MOVA the last instruction in the clause */
> +	if ((bc->cf_last->ndw>>1) >= 110)
> +		bc->force_add_cf = 1;
> +
> +	memset(&alu, 0, sizeof(alu));
> +	alu.inst = bc->chip_class >= EVERGREEN ?
> +			EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT :
> +			V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT;

Shouldn't this be
alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_INT);
?

Can't comment on the rest

Kind regards,
Kai Wasserbäch