[Mesa-dev] [PATCH] i965/gen6: Manipulate state batches for HiZ meta-ops [v2]

[Chad Versace]

A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.

v2: [anholt] Do not special-case the
    3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit for HiZ in
    gen6_upload_depth_stencil(). The HiZ meta-op sets ctx->Depth.Test, so
    just read the value from that.

CC: Eric Anholt <eric at anholt.net>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_draw.c          |    9 ++++++++-
 src/mesa/drivers/dri/i965/gen6_clip_state.c   |   17 +++++++++++++++++
 src/mesa/drivers/dri/i965/gen6_depthstencil.c |    8 ++++++--
 src/mesa/drivers/dri/i965/gen6_sf_state.c     |   15 +++++++++++++--
 src/mesa/drivers/dri/i965/gen6_wm_state.c     |   17 +++++++++++++++++
 5 files changed, 61 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 1571fb7..d2ae087 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -117,10 +117,17 @@ static void brw_set_prim(struct brw_context *brw,
 static void gen6_set_prim(struct brw_context *brw,
                           const struct _mesa_prim *prim)
 {
-   uint32_t hw_prim = prim_to_hw_prim[prim->mode];
+   uint32_t hw_prim;
 
    DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim->mode));
 
+   if (brw->hiz.op) {
+      assert(prim->mode == GL_TRIANGLES);
+      hw_prim = _3DPRIM_RECTLIST;
+   } else {
+      hw_prim = prim_to_hw_prim[prim->mode];
+   }
+
    if (hw_prim != brw->primitive) {
       brw->primitive = hw_prim;
       brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c
index b3bb8ae..0fb588b 100644
--- a/src/mesa/drivers/dri/i965/gen6_clip_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c
@@ -67,6 +67,23 @@ upload_clip_state(struct brw_context *brw)
          GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE;
    }
 
+   if (brw->hiz.op) {
+      /* HiZ operations emit a rectangle primitive, which requires clipping to
+       * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
+       * Section 1.3 3D Primitives Overview:
+       *    RECTLIST:
+       *    Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
+       *    Mode should be set to a value other than CLIPMODE_NORMAL.
+       */
+      BEGIN_BATCH(4);
+      OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      ADVANCE_BATCH();
+      return;
+   }
+
    if (!ctx->Transform.DepthClamp)
       depth_clamp = GEN6_CLIP_Z_TEST;
 
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 72e8687..b52c1b2 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -77,8 +77,12 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
    }
 
    /* _NEW_DEPTH */
-   if (ctx->Depth.Test) {
-      ds->ds2.depth_test_enable = 1;
+   if (ctx->Depth.Test || brw->hiz.op) {
+      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
+      assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE   || !ctx->Depth.Test);
+      assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR   || !ctx->Depth.Test);
+
+      ds->ds2.depth_test_enable = ctx->Depth.Test;
       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
       ds->ds2.depth_write_enable = ctx->Depth.Mask;
    }
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 67119d8..5d95259 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -147,8 +147,19 @@ upload_sf_state(struct brw_context *brw)
       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
       urb_entry_read_length << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
       urb_entry_read_offset << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
-   dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
-      GEN6_SF_STATISTICS_ENABLE;
+
+   dw2 = GEN6_SF_STATISTICS_ENABLE;
+
+   /* Enable viewport transform only if no HiZ operation is progress
+    *
+    * From page 11 of the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
+    * Primitives Overview":
+    *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
+    *     use of screen- space coordinates).
+    */
+   if (!brw->hiz.op)
+      dw2 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE;
+
    dw3 = 0;
    dw4 = 0;
    dw16 = 0;
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 271a9ae..1ee21e0 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -147,6 +147,23 @@ upload_wm_state(struct brw_context *brw)
    dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 	   GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 
+   switch (brw->hiz.op) {
+   case BRW_HIZ_OP_NONE:
+      break;
+   case BRW_HIZ_OP_DEPTH_CLEAR:
+      dw4 |= GEN6_WM_DEPTH_CLEAR;
+      break;
+   case BRW_HIZ_OP_DEPTH_RESOLVE:
+      dw4 |= GEN6_WM_DEPTH_RESOLVE;
+      break;
+   case BRW_HIZ_OP_HIZ_RESOLVE:
+      dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE;
+      break;
+   default:
+      assert(0);
+      break;
+   }
+
    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 
    /* CACHE_NEW_WM_PROG */
-- 
1.7.7.1