[Mesa-dev] [PATCH 36/36] i965: GS: Use the VUE map to compute URB size.

[Paul Berry]

The previous computation had two bugs: (a) it used a formula based on
Gen5 for Gen6 and Gen7 as well. (b) it failed to account for the fact
that PSIZ is stored in the VUE header.  Fortunately, both bugs caused
it to compute a URB size that was too large, which was benign.  This
patch computes the URB size directly from the VUE map, so it gets the
result correct in all circumstances.
---
 src/mesa/drivers/dri/i965/brw_gs.c |   23 +++++++++++------------
 src/mesa/drivers/dri/i965/brw_gs.h |    9 ++++-----
 2 files changed, 15 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index f4656af..ddeb5bf 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -62,17 +62,11 @@ static void compile_gs_prog( struct brw_context *brw,
    memset(&c, 0, sizeof(c));
    
    c.key = *key;
-   /* Need to locate the two positions present in vertex + header.
-    * These are currently hardcoded:
-    */
-   c.nr_attrs = brw_count_bits(c.key.attrs);
-
-   if (intel->gen >= 5)
-       c.nr_regs = (c.nr_attrs + 1) / 2 + 3;  /* are vertices packed, or reg-aligned? */
-   else
-       c.nr_regs = (c.nr_attrs + 1) / 2 + 1;  /* are vertices packed, or reg-aligned? */
-
-   c.nr_bytes = c.nr_regs * REG_SIZE;
+   /* The geometry shader needs to access the entire VUE. */
+   struct brw_vue_map vue_map;
+   brw_compute_vue_map(&vue_map, intel, c.key.nr_userclip,
+                       c.key.do_twoside_color, c.key.attrs);
+   c.nr_regs = (vue_map.num_slots + 1)/2;
 
    mem_ctx = NULL;
    
@@ -158,6 +152,7 @@ static void populate_key( struct brw_context *brw,
 
    /* _NEW_LIGHT */
    key->pv_first = (ctx->Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION);
+   key->do_twoside_color = (ctx->Light.Enabled && ctx->Light.Model.TwoSide);
    if (key->primitive == GL_QUADS && ctx->Light.ShadeModel != GL_FLAT) {
       /* Provide consistent primitive order with brw_set_prim's
        * optimization of single quads to trifans.
@@ -165,6 +160,9 @@ static void populate_key( struct brw_context *brw,
       key->pv_first = GL_TRUE;
    }
 
+   /* _NEW_TRANSFORM */
+   key->nr_userclip = brw_count_bits(ctx->Transform.ClipPlanesEnabled);
+
    key->need_gs_prog = (intel->gen >= 6)
       ? 0
       : (brw->primitive == GL_QUADS ||
@@ -198,7 +196,8 @@ static void prepare_gs_prog(struct brw_context *brw)
 
 const struct brw_tracked_state brw_gs_prog = {
    .dirty = {
-      .mesa  = _NEW_LIGHT,
+      .mesa  = (_NEW_LIGHT |
+                _NEW_TRANSFORM),
       .brw   = BRW_NEW_PRIMITIVE,
       .cache = CACHE_NEW_VS_PROG
    },
diff --git a/src/mesa/drivers/dri/i965/brw_gs.h b/src/mesa/drivers/dri/i965/brw_gs.h
index c33528e..b369e7d 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.h
+++ b/src/mesa/drivers/dri/i965/brw_gs.h
@@ -44,7 +44,9 @@ struct brw_gs_prog_key {
    GLuint primitive:4;
    GLuint pv_first:1;
    GLuint need_gs_prog:1;
-   GLuint pad:26;
+   GLuint nr_userclip:4;
+   GLuint do_twoside_color:1;
+   GLuint pad:21;
 };
 
 struct brw_gs_compile {
@@ -58,11 +60,8 @@ struct brw_gs_compile {
       struct brw_reg temp;
    } reg;
 
-   /* 3 different ways of expressing vertex size:
-    */
-   GLuint nr_attrs;
+   /* Number of registers used to store vertex data */
    GLuint nr_regs;
-   GLuint nr_bytes;
 };
 
 #define ATTR_SIZE  (4*4)
-- 
1.7.6