[Mesa-dev] [RFC] [PATCH 2/2] i965: setup the edge flag enable bit in VE on SNB+

[Yuanhan Liu]

This patch is just for RFC, as I am not sure it's the right way to setup
the edge flag enable bit in Vertex Element struture. Setting up this
bit, according to Bspec, need do:
 1. Edge flags are supported for the following primitives
    	3DPRIM_TRILIST*
	3DPRIM_TRISTRIP*
	3DPRIM_TRIFAN*
	3DPRIM_POLYGON
 2. This bit must only be ENABLED on the last valid VERTEX_ELEMENT
    structure.

 3. When set, Component 0 Control must be set to VFCOMP_STORE_SRC, and
    Component 1-3 Control must be set to VFCOMP_NOSTORE.

 4. The Source Element Format must be set to the UINT format.

This patch did 1, 2, but didn't do 3, 4. As it simply seems wrong to me
just change the last vetex element's component setting and source
element format.

Thoughts?

BTW, this patch fix the oglc pntrast fail on SNB(haven't tested it on
IVB yet).

Signed-off-by: Yuanhan Liu <yuanhan.liu at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_defines.h     |    1 +
 src/mesa/drivers/dri/i965/brw_draw_upload.c |   15 +++++++++++++++
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 5f34939..c8a091c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -945,6 +945,7 @@ enum opcode {
 # define BRW_VE0_INDEX_SHIFT		27
 # define GEN6_VE0_INDEX_SHIFT		26
 # define BRW_VE0_FORMAT_SHIFT		16
+# define GEN6_VE0_EDGE_FLAG_ENABLE	(1 << 15)
 # define BRW_VE0_VALID			(1 << 26)
 # define GEN6_VE0_VALID			(1 << 25)
 # define BRW_VE0_SRC_OFFSET_SHIFT	0
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 7bc69c6..093a46f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -609,6 +609,7 @@ static void brw_emit_vertices(struct brw_context *brw)
       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
       uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
+      int edge_flag_enable;
 
       switch (input->glarray->Size) {
       case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
@@ -618,10 +619,24 @@ static void brw_emit_vertices(struct brw_context *brw)
 	 break;
       }
 
+      edge_flag_enable = 0;
+      /*
+       * According to Bspec, the edge flag enable bit should be set
+       * at the last valid vertex element structure
+       */
+      if (intel->gen >= 6 && i == brw->vb.nr_enabled - 1 &&
+          (brw->vs.prog_data->inputs_read & VERT_BIT_EDGEFLAG) &&
+	   (brw->hw_prim == _3DPRIM_TRILIST ||
+	    brw->hw_prim == _3DPRIM_TRISTRIP ||
+	    brw->hw_prim == _3DPRIM_TRIFAN ||
+	    brw->hw_prim == _3DPRIM_POLYGON)) {
+         edge_flag_enable = GEN6_VE0_EDGE_FLAG_ENABLE;
+      }
       if (intel->gen >= 6) {
 	 OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
 		   GEN6_VE0_VALID |
 		   (format << BRW_VE0_FORMAT_SHIFT) |
+		   edge_flag_enable |
 		   (input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
       } else {
 	 OUT_BATCH((input->buffer << BRW_VE0_INDEX_SHIFT) |
-- 
1.7.4.4