[Mesa-dev] [PATCH 3/7] i965/fs: Add support for bit-shift operations.

[Kenneth Graunke]

On 09/27/2011 03:08 PM, Eric Anholt wrote:
> ---
>  src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index df43be0..d8ce47b 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -445,8 +445,14 @@ fs_visitor::visit(ir_expression *ir)
>        break;
>  
>     case ir_binop_lshift:
> +      inst = emit(BRW_OPCODE_SHL, this->result, op[0], op[1]);
> +      break;
> +
>     case ir_binop_rshift:
> -      assert(!"GLSL 1.30 features unsupported");
> +      if (ir->type->base_type == GLSL_TYPE_INT)
> +	 inst = emit(BRW_OPCODE_ASR, this->result, op[0], op[1]);
> +      else
> +	 inst = emit(BRW_OPCODE_SHR, this->result, op[0], op[1]);
>        break;
>     }
>  }

I'm feeling slightly paranoid about SHR's restrictions:

"This instruction only takes on unsigned sources. When <src0> contains
 unsigned integers, no source modifier is allowed. <src0> is only
 allowed to be signed integer if source modifier (abs) is used. Note:
 for unsigned sources, the behavior of shr and asr are effectively the
 same."

I see nothing guaranteeing that op[1] has register type UD.  I'm not
positive what would happen if you gave it a D (signed) register.
Undefined results are okay according to the GLSL spec.  GPU hang is not.

Smashing it to be type UD would work, but may be unnecessary.