[Mesa-dev] [PATCH 3/7] i965/fs: Add support for bit-shift operations.
eric at anholt.net
Wed Sep 28 10:33:45 PDT 2011
On Wed, 28 Sep 2011 01:21:50 -0700, Kenneth Graunke <kenneth at whitecape.org> wrote:
> On 09/27/2011 03:08 PM, Eric Anholt wrote:
> > ---
> > src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 8 +++++++-
> > 1 files changed, 7 insertions(+), 1 deletions(-)
> > diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> > index df43be0..d8ce47b 100644
> > --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> > +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> > @@ -445,8 +445,14 @@ fs_visitor::visit(ir_expression *ir)
> > break;
> > case ir_binop_lshift:
> > + inst = emit(BRW_OPCODE_SHL, this->result, op, op);
> > + break;
> > +
> > case ir_binop_rshift:
> > - assert(!"GLSL 1.30 features unsupported");
> > + if (ir->type->base_type == GLSL_TYPE_INT)
> > + inst = emit(BRW_OPCODE_ASR, this->result, op, op);
> > + else
> > + inst = emit(BRW_OPCODE_SHR, this->result, op, op);
> > break;
> > }
> > }
> I'm feeling slightly paranoid about SHR's restrictions:
> "This instruction only takes on unsigned sources. When <src0> contains
> unsigned integers, no source modifier is allowed. <src0> is only
> allowed to be signed integer if source modifier (abs) is used. Note:
> for unsigned sources, the behavior of shr and asr are effectively the
> I see nothing guaranteeing that op has register type UD. I'm not
> positive what would happen if you gave it a D (signed) register.
> Undefined results are okay according to the GLSL spec. GPU hang is not.
> Smashing it to be type UD would work, but may be unnecessary.
Those restrictions sound to me like what they really mean to say is "we
only shift as both pieces are UD", which would make sense for the
instruction. The text just above your quote says "The amount of bit
shift is provided by <src1> where only the 5 LSBs of each channel of
<src1> are used as an unsigned integer value."
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