[Mesa-dev] [PATCH] r600g: bypass alpha for integer types
Dave Airlie
airlied at gmail.com
Sun Apr 22 12:52:30 PDT 2012
From: Dave Airlie <airlied at redhat.com>
This moves the alpha test control to derived state and disables alpha
testing for integer fbs.
fbo-blending test in piglit gets further when we do this (not a pass
but less fail).
Signed-off-by: Dave Airlie <airlied at redhat.com>
---
src/gallium/drivers/r600/evergreen_state.c | 7 ++++++-
src/gallium/drivers/r600/r600_pipe.h | 3 +++
src/gallium/drivers/r600/r600_state.c | 7 ++++++-
src/gallium/drivers/r600/r600_state_common.c | 7 +++++++
4 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 941744e..eea3970 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -804,11 +804,11 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
/* misc */
db_render_control = 0;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, NULL, 0);
return rstate;
@@ -1442,6 +1442,11 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
blend_bypass = 1;
}
+ if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT)
+ rctx->fb_sx_alpha_test_control = S_028410_ALPHA_TEST_BYPASS(1);
+ else
+ rctx->fb_sx_alpha_test_control = 0;
+
color_info |= S_028C70_FORMAT(format) |
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(blend_clamp) |
diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 1040a45..a8e33e3 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -161,6 +161,7 @@ struct r600_pipe_dsa {
ubyte valuemask[2];
ubyte writemask[2];
bool is_flush;
+ unsigned sx_alpha_test_control;
};
struct r600_vertex_element
@@ -262,6 +263,8 @@ struct r600_context {
struct pipe_framebuffer_state framebuffer;
unsigned cb_target_mask;
unsigned fb_cb_shader_mask;
+ unsigned sx_alpha_test_control;
+ unsigned fb_sx_alpha_test_control;
unsigned cb_shader_mask;
unsigned cb_color_control;
unsigned pa_sc_line_stipple;
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 6290aa5..626ff2c 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -805,9 +805,9 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
alpha_ref = fui(state->alpha.ref_value);
}
+ dsa->sx_alpha_test_control = alpha_test_control & 0xff;
dsa->alpha_ref = alpha_ref;
- r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
return rstate;
}
@@ -1473,6 +1473,11 @@ static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
blend_bypass = 1;
}
+ if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
+ rctx->fb_sx_alpha_test_control = S_028410_ALPHA_TEST_BYPASS(1);
+ else
+ rctx->fb_sx_alpha_test_control = 0;
+
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_BYPASS(blend_bypass) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c
index 6d4f3ef..69743f2 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -246,6 +246,8 @@ void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
return;
rstate = &dsa->rstate;
rctx->states[rstate->id] = rstate;
+ rctx->sx_alpha_test_control &= ~0xff;
+ rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
rctx->alpha_ref = dsa->alpha_ref;
rctx->alpha_ref_dirty = true;
r600_context_pipe_state_set(rctx, rstate);
@@ -712,6 +714,9 @@ static void r600_update_derived_state(struct r600_context *rctx)
rctx->cb_shader_mask = rctx->ps_shader->ps_cb_shader_mask | rctx->fb_cb_shader_mask;
else
rctx->cb_shader_mask = rctx->fb_cb_shader_mask;
+
+ rctx->sx_alpha_test_control &= ~(1 << 8);
+ rctx->sx_alpha_test_control |= rctx->fb_sx_alpha_test_control;
}
static unsigned r600_conv_prim_to_gs_out(unsigned mode)
@@ -805,6 +810,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_02823C_CB_SHADER_MASK, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
+ r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
@@ -826,6 +832,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_shader_mask);
r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
+ r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
--
1.7.7.6
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