[Mesa-dev] [PATCH 1/3] radeon/llvm: Split Word0 and Word1 in Export instruction
Vincent Lejeune
vljn at ovi.com
Sat Dec 8 09:10:17 PST 2012
---
.../AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp | 4 +-
lib/Target/AMDGPU/R600ISelLowering.cpp | 6 +-
lib/Target/AMDGPU/R600Instructions.td | 99 ++++++++++++----------
3 files changed, 60 insertions(+), 49 deletions(-)
diff --git a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
index 756f945..cb89ebe 100644
--- a/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
+++ b/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
@@ -174,8 +174,8 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
Emit(InstWord2, OS);
break;
}
- case AMDGPU::EG_Export:
- case AMDGPU::R600_Export: {
+ case AMDGPU::EG_ExportSwz:
+ case AMDGPU::R600_ExportSwz:
uint64_t Inst = getBinaryCodeForInstr(MI, Fixups);
EmitByte(INSTR_EXPORT, OS);
Emit(Inst, OS);
diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 2218359..7787599 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -329,12 +329,12 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
return BB;
}
- case AMDGPU::EG_Export:
- case AMDGPU::R600_Export: {
+ case AMDGPU::EG_ExportSwz:
+ case AMDGPU::R600_ExportSwz: {
bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
if (!EOP)
return BB;
- unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_Export)? 84 : 40;
+ unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1))
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 880c05b..0afbd9d 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -478,6 +478,38 @@ def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
[SDNPHasChain, SDNPSideEffect]>;
+class ExportWord0 {
+ field bits<32> Word0;
+
+ bits<13> arraybase;
+ bits<2> type;
+ bits<7> gpr;
+ bits<2> elem_size;
+
+ let Word0{12-0} = arraybase;
+ let Word0{14-13} = type;
+ let Word0{21-15} = gpr;
+ let Word0{22} = 0; // RW_REL
+ let Word0{29-23} = 0; // INDEX_GPR
+ let Word0{31-30} = elem_size;
+}
+
+class ExportSwzWord1 {
+ field bits<32> Word1;
+
+ bits<3> sw_x;
+ bits<3> sw_y;
+ bits<3> sw_z;
+ bits<3> sw_w;
+ bits<1> eop;
+ bits<8> inst;
+
+ let Word1{2-0} = sw_x;
+ let Word1{5-3} = sw_y;
+ let Word1{8-6} = sw_z;
+ let Word1{11-9} = sw_w;
+}
+
multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
def : Pat<(int_R600_store_pixel_depth R600_Reg32:$reg),
(ExportInst
@@ -506,35 +538,16 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
let isTerminator = 1, usesCustomInserter = 1 in {
-class ExportInst : InstR600ISA<(
+class ExportSwzInst : InstR600ISA<(
outs),
- (ins R600_Reg128:$src, i32imm:$type, i32imm:$arraybase,
+ (ins R600_Reg128:$gpr, i32imm:$type, i32imm:$arraybase,
i32imm:$sw_x, i32imm:$sw_y, i32imm:$sw_z, i32imm:$sw_w, i32imm:$inst,
i32imm:$eop),
- !strconcat("EXPORT", " $src"),
- []> {
- bits<13> arraybase;
- bits<2> type;
- bits<7> src;
-
- bits<3> sw_x;
- bits<3> sw_y;
- bits<3> sw_z;
- bits<3> sw_w;
-
- bits<1> eop;
- bits<8> inst;
-
- let Inst{12-0} = arraybase;
- let Inst{14-13} = type;
- let Inst{21-15} = src;
- let Inst{22} = 0; // RW_REL
- let Inst{29-23} = 0; // INDEX_GPR
- let Inst{31-30} = 3; // ELEM_SIZE
- let Inst{34-32} = sw_x;
- let Inst{37-35} = sw_y;
- let Inst{40-38} = sw_z;
- let Inst{43-41} = sw_w;
+ !strconcat("EXPORT", " $gpr"),
+ []>, ExportWord0, ExportSwzWord1 {
+ let elem_size = 3;
+ let Inst{31-0} = Word0;
+ let Inst{63-32} = Word1;
}
} // End isTerminator = 1, usesCustomInserter = 1
@@ -978,18 +991,17 @@ let Predicates = [isR600] in {
defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
- def R600_Export : ExportInst {
- let Inst{52-49} = 1; // BURST_COUNT
- let Inst{53} = eop;
- let Inst{54} = 1; // VALID_PIXEL_MODE
- let Inst{62-55} = inst;
- let Inst{63} = 1; // BARRIER
- }
-
def : Pat<(fsqrt R600_Reg32:$src),
(MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_r600 R600_Reg32:$src))>;
- defm : ExportPattern<R600_Export, 39>;
+ def R600_ExportSwz : ExportSwzInst {
+ let Word1{20-17} = 1; // BURST_COUNT
+ let Word1{21} = eop;
+ let Word1{22} = 1; // VALID_PIXEL_MODE
+ let Word1{30-23} = inst;
+ let Word1{31} = 1; // BARRIER
+ }
+ defm : ExportPattern<R600_ExportSwz, 39>;
}
// Helper pattern for normalizing inputs to triginomic instructions for R700+
@@ -1124,16 +1136,15 @@ let hasSideEffects = 1 in {
def : Pat<(fp_to_uint R600_Reg32:$src0),
(FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
- def EG_Export : ExportInst {
- let Inst{51-48} = 1; // BURST_COUNT
- let Inst{52} = 1; // VALID_PIXEL_MODE
- let Inst{53} = eop;
- let Inst{61-54} = inst;
- let Inst{62} = 0; // MARK
- let Inst{63} = 1; // BARRIER
+ def EG_ExportSwz : ExportSwzInst {
+ let Word1{19-16} = 1; // BURST_COUNT
+ let Word1{20} = 1; // VALID_PIXEL_MODE
+ let Word1{21} = eop;
+ let Word1{29-22} = inst;
+ let Word1{30} = 0; // MARK
+ let Word1{31} = 1; // BARRIER
}
-
- defm : ExportPattern<EG_Export, 83>;
+ defm : ExportPattern<EG_ExportSwz, 83>;
//===----------------------------------------------------------------------===//
// Memory read/write instructions
--
1.8.0.1
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