[Mesa-dev] [PATCH 2/3] radeon/llvm: Add a field for Export node (compMask) and factorise code handling store intrinsic

[Vincent Lejeune]

---
 lib/Target/AMDGPU/R600ISelLowering.cpp | 91 ++++++++++++++++++++--------------
 lib/Target/AMDGPU/R600Instructions.td  |  9 ++--
 2 files changed, 58 insertions(+), 42 deletions(-)

diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
index 7787599..1b6d909 100644
--- a/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -360,6 +360,57 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
 using namespace llvm::Intrinsic;
 using namespace llvm::AMDGPUIntrinsic;
 
+static SDValue
+InsertScalarToRegisterExport(SelectionDAG &DAG, DebugLoc DL, SDNode **ExportMap,
+    unsigned Slot, unsigned Channel, unsigned Inst, unsigned Type,
+    SDValue Scalar, SDValue Chain) {
+  if (!ExportMap[Slot]) {
+    SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
+      DL, MVT::v4f32,
+      DAG.getUNDEF(MVT::v4f32),
+      Scalar,
+      DAG.getConstant(Channel, MVT::i32));
+
+    unsigned Mask = 1 << Channel;
+
+    const SDValue Ops[] = {Chain, Vector, DAG.getConstant(Inst, MVT::i32),
+        DAG.getConstant(Type, MVT::i32), DAG.getConstant(Slot, MVT::i32),
+        DAG.getConstant(Mask, MVT::i32)};
+
+    SDValue Res =  DAG.getNode(
+        AMDGPUISD::EXPORT,
+        DL,
+        MVT::Other,
+        Ops, 6);
+     ExportMap[Slot] = Res.getNode();
+     return Res;
+  }
+
+  SDNode *ExportInstruction = (SDNode *) ExportMap[Slot] ;
+  SDValue PreviousVector = ExportInstruction->getOperand(1);
+  SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
+      DL, MVT::v4f32,
+      PreviousVector,
+      Scalar,
+      DAG.getConstant(Channel, MVT::i32));
+
+  unsigned Mask = dyn_cast<ConstantSDNode>(ExportInstruction->getOperand(5))
+      ->getZExtValue();
+  Mask |= (1 << Channel);
+
+  const SDValue Ops[] = {ExportInstruction->getOperand(0), Vector,
+      DAG.getConstant(Inst, MVT::i32),
+      DAG.getConstant(Type, MVT::i32),
+      DAG.getConstant(Slot, MVT::i32),
+      DAG.getConstant(Mask, MVT::i32)};
+
+  DAG.UpdateNodeOperands(ExportInstruction,
+      Ops, 6);
+
+  return Chain;
+
+}
+
 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
   default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
@@ -391,48 +442,14 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
       MachineFunction &MF = DAG.getMachineFunction();
       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
       int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
-      unsigned Slot = RegIndex / 4;
 
       SDNode **OutputsMap = MFI->Outputs;
+      return InsertScalarToRegisterExport(DAG, Op.getDebugLoc(), OutputsMap,
+          RegIndex / 4, RegIndex % 4, 0, 0, Op.getOperand(2),
+          Chain);
 
-      if (!OutputsMap[Slot]) {
-        SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
-          Op.getDebugLoc(), MVT::v4f32,
-          DAG.getUNDEF(MVT::v4f32),
-          Op.getOperand(2),
-          DAG.getConstant(RegIndex % 4, MVT::i32));
-
-        const SDValue Ops[8] = {Chain, Vector, DAG.getConstant(0, MVT::i32),
-            DAG.getConstant(Slot, MVT::i32), DAG.getConstant(0, MVT::i32),
-            DAG.getConstant(1, MVT::i32), DAG.getConstant(2, MVT::i32),
-            DAG.getConstant(3, MVT::i32)};
-
-        SDValue Res =  DAG.getNode(
-            AMDGPUISD::EXPORT,
-            Op.getDebugLoc(),
-            MVT::Other,
-            Ops, 8);
-         OutputsMap[Slot] = Res.getNode();
-         return Res;
       }
 
-      SDNode *ExportInstruction = (SDNode *) OutputsMap[Slot] ;
-      SDValue PreviousVector = ExportInstruction->getOperand(1);
-      SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
-          Op.getDebugLoc(), MVT::v4f32,
-          PreviousVector,
-          Op.getOperand(2),
-          DAG.getConstant(RegIndex % 4, MVT::i32));
-
-      const SDValue Ops[8] = {ExportInstruction->getOperand(0), Vector, DAG.getConstant(0, MVT::i32),
-          DAG.getConstant(Slot, MVT::i32), DAG.getConstant(0, MVT::i32),
-          DAG.getConstant(1, MVT::i32), DAG.getConstant(2, MVT::i32),
-          DAG.getConstant(3, MVT::i32)};
-
-      DAG.UpdateNodeOperands(ExportInstruction,
-          Ops, 8);
-
-      return Chain;
     }
     // default for switch(IntrinsicID)
     default: break;
diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
index 0afbd9d..7c1df72 100644
--- a/lib/Target/AMDGPU/R600Instructions.td
+++ b/lib/Target/AMDGPU/R600Instructions.td
@@ -473,7 +473,7 @@ def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
 // Export Instructions
 //===----------------------------------------------------------------------===//
 
-def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
+def ExportType : SDTypeProfile<0, 5, [SDTCisFP<0>, SDTCisInt<1>]>;
 
 def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
   [SDNPHasChain, SDNPSideEffect]>;
@@ -528,11 +528,10 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
         (v4f32 (IMPLICIT_DEF)), 0, 0, 7, 7, 7, 7, cf_inst, 0)
   >;
 
-  def : Pat<(EXPORT (v4f32 R600_Reg128:$src),
-    (i32 imm:$type), (i32 imm:$arraybase),
-    (i32 imm:$sw_x), (i32 imm:$sw_y), (i32 imm:$sw_z), (i32 imm:$sw_w)),
+  def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 0),
+    (i32 imm:$type), (i32 imm:$arraybase), (i32 imm)),
         (ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
-        imm:$sw_x, imm:$sw_y, imm:$sw_z, imm:$sw_w, cf_inst, 0)
+        0, 1, 2, 3, cf_inst, 0)
   >;
 }
 
-- 
1.8.0.1