[Mesa-dev] [PATCH 4/6] i965: Account for offsets when emitting SURFACE_STATE.

[Abdiel Janulgue]

If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.

Signed-off-by: Abdiel Janulgue <abdiel.janulgue at linux.intel.com>
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  |   12 +++++++++++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |   12 ++++++++++--
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a7866d5..6389fe0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -788,6 +788,7 @@ brw_update_texture_surface(struct gl_context *ctx,
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    uint32_t *surf;
    int width, height, depth;
+   uint32_t tile_x, tile_y;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
@@ -821,7 +822,16 @@ brw_update_texture_surface(struct gl_context *ctx,
 
    surf[4] = 0;
 
-   surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
+   intel_miptree_get_tile_offsets(intelObj->mt, 0, &tile_x, &tile_y);
+   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   assert(tile_x % 4 == 0);
+   assert(tile_y % 2 == 0);
+   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
+	      (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+	      (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 466a038..6caf787 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -302,6 +302,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    struct gen7_surface_state *surf;
    int width, height, depth;
+   uint32_t tile_x, tile_y;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
@@ -359,12 +360,19 @@ gen7_update_texture_surface(struct gl_context *ctx,
 
    /* ss4: ignored? */
 
+   intel_miptree_get_tile_offsets(intelObj->mt, 0, &tile_x, &tile_y);
+   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   assert(tile_x % 4 == 0);
+   assert(tile_y % 2 == 0);
    surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
    surf->ss5.min_lod = 0;
+   surf->ss5.x_offset = tile_x / 4;
+   surf->ss5.y_offset = tile_y / 2;
 
    /* ss5 remaining fields:
-    * - x_offset (N/A for textures?)
-    * - y_offset (ditto)
     * - cache_control
     */
 
-- 
1.7.9.5