[Mesa-dev] [PATCH 05/11] i965: Add missing BRW_NEW_BATCH dirty bit to the Gen6+ URB atoms.

[Kenneth Graunke]

Without MI_SET_CONTEXT, there's no guarantee that another program hasn't
reprogram the GPU's URB state since our last batch.  We need to submit
it every time.

This is especially important now that we actually reprogram the URB
layout on Gen6 based on whether or not we're using transform feedback.

Found by inspection.

NOTE: This is a candidate for the 7.11 branch.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
---
 src/mesa/drivers/dri/i965/gen6_urb.c |    2 +-
 src/mesa/drivers/dri/i965/gen7_urb.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c
index 2d69cbe..16d6054 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -118,7 +118,7 @@ gen6_upload_urb( struct brw_context *brw )
 const struct brw_tracked_state gen6_urb = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_CONTEXT,
+      .brw = BRW_NEW_CONTEXT | BRW_NEW_BATCH,
       .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
    },
    .emit = gen6_upload_urb,
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index e53fcb7..12df2d4 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -115,7 +115,7 @@ gen7_upload_urb(struct brw_context *brw)
 const struct brw_tracked_state gen7_urb = {
    .dirty = {
       .mesa = 0,
-      .brw = BRW_NEW_CONTEXT,
+      .brw = BRW_NEW_CONTEXT | BRW_NEW_BATCH,
       .cache = (CACHE_NEW_VS_PROG | CACHE_NEW_GS_PROG),
    },
    .emit = gen7_upload_urb,
-- 
1.7.7.5