[Mesa-dev] [PATCH 1/9] intel gen4-5: fix the vue view in the fs.

[Olivier Galibert]

In some cases the fragment shader view of the vue registers was out of
sync with the builder.  This fixes it.

Signed-off-by: Olivier Galibert <galibert at pobox.com>
---
 src/mesa/drivers/dri/i965/brw_fs.cpp     |    9 ++++++++-
 src/mesa/drivers/dri/i965/brw_wm_pass2.c |   10 +++++++++-
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b3b25cc..3f98137 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -972,8 +972,15 @@ fs_visitor::calculate_urb_setup()
 	 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
 	    int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
 
+	    /* The back color slot is skipped when the front color is
+	     * also written to.  In addition, some slots can be
+	     * written in the vertex shader and not read in the
+	     * fragment shader.  So the register number must always be
+	     * incremented, mapped or not.
+	     */
 	    if (fp_index >= 0)
-	       urb_setup[fp_index] = urb_next++;
+	       urb_setup[fp_index] = urb_next;
+	    urb_next++;
 	 }
       }
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 27c0a94..eacf7c0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -97,8 +97,16 @@ static void init_registers( struct brw_wm_compile *c )
 	    int fp_index = _mesa_vert_result_to_frag_attrib(j);
 
 	    nr_interp_regs++;
+
+	    /* The back color slot is skipped when the front color is
+	     * also written to.  In addition, some slots can be
+	     * written in the vertex shader and not read in the
+	     * fragment shader.  So the register number must always be
+	     * incremented, mapped or not.
+	     */
 	    if (fp_index >= 0)
-	       prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
+	       prealloc_reg(c, &c->payload.input_interp[fp_index], i);
+            i++;
 	 }
       }
       assert(nr_interp_regs >= 1);
-- 
1.7.10.280.gaa39