[Mesa-dev] [PATCH 2/4] i965: we want 64bit writes for depth count

[Daniel Vetter]

... and the hardware seems to take the lenght of the pipe control
command to indicate whether the write is 64bit or 32bit. Which makes
sense for immediate writes.

I've discovered this by writing a pattern into the query object bo and
noticing that the high 32bits are left intact, even on those pipe
control writes that seemingly worked.

v2: use | (5-2) to denote 5 dword long PIPE_CONTROL commands, as
suggested by Kenneth Graunke.
---
 src/mesa/drivers/dri/i965/brw_queryobj.c |   10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index 52db050..8049580 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -337,7 +337,7 @@ brw_emit_query_begin(struct brw_context *brw)
       return;
 
    if (intel->gen >= 6) {
-       BEGIN_BATCH(12);
+       BEGIN_BATCH(13);
 
        /* Workaround: A non-zero post-sync op (i.e. the DEPTH_COUNT write below
 	* needs a pipe control with CS_STALL set beforehand.
@@ -350,13 +350,14 @@ brw_emit_query_begin(struct brw_context *brw)
        OUT_BATCH(0);
 
        /* The actual DEPTH_COUNT write. */
-       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 3));
        OUT_BATCH(PIPE_CONTROL_WRITE_DEPTH_COUNT);
        OUT_RELOC(brw->query.bo,
 	         I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 		 PIPE_CONTROL_GLOBAL_GTT_WRITE |
 		 ((brw->query.index * 2) * sizeof(uint64_t)));
        OUT_BATCH(0);
+       OUT_BATCH(0);
 
        /* We need to emit depth stall to get the right value for the depth
 	* count. As a workaround this needs a preceeding pipe control with a
@@ -407,7 +408,7 @@ brw_emit_query_end(struct brw_context *brw)
       return;
 
    if (intel->gen >= 6) {
-       BEGIN_BATCH(12);
+       BEGIN_BATCH(13);
 
        /* Workaround: A non-zero post-sync op (i.e. the DEPTH_COUNT write below
 	* needs a pipe control with CS_STALL set beforehand.
@@ -420,13 +421,14 @@ brw_emit_query_end(struct brw_context *brw)
        OUT_BATCH(0);
 
        /* The actual DEPTH_COUNT write. */
-       OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+       OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 3));
        OUT_BATCH(PIPE_CONTROL_WRITE_DEPTH_COUNT);
        OUT_RELOC(brw->query.bo,
 	         I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 		 PIPE_CONTROL_GLOBAL_GTT_WRITE |
 		 ((brw->query.index * 2 + 1) * sizeof(uint64_t)));
        OUT_BATCH(0);
+       OUT_BATCH(0);
 
        /* We need to emit depth stall to get the right value for the depth
 	* count. As a workaround this needs a preceeding pipe control with a
-- 
1.7.10.4