[Mesa-dev] [PATCH 4/4] i965: make the length for PIPE_CONTROL explicit
Daniel Vetter
daniel.vetter at ffwll.ch
Fri Jul 20 13:48:51 PDT 2012
PIPE_CONTROL has variable length, depending upon gen and whether we
write out 32bit or 64bit. So make this explicit.
Suggested by Kenneth Graunke.
---
src/mesa/drivers/dri/i965/brw_queryobj.c | 22 +++++++++++-----------
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +-
src/mesa/drivers/dri/intel/intel_batchbuffer.c | 16 ++++++++--------
src/mesa/drivers/dri/intel/intel_reg.h | 2 +-
4 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c
index a6b3e22..663344a 100644
--- a/src/mesa/drivers/dri/i965/brw_queryobj.c
+++ b/src/mesa/drivers/dri/i965/brw_queryobj.c
@@ -137,7 +137,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q)
* needs a pipe control with CS_STALL set beforehand.
* Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
* like the kernel. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0);
@@ -156,7 +156,7 @@ brw_begin_query(struct gl_context *ctx, struct gl_query_object *q)
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
- PIPE_CONTROL_WRITE_TIMESTAMP);
+ PIPE_CONTROL_WRITE_TIMESTAMP | (4 - 2));
OUT_RELOC(query->bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE |
@@ -219,7 +219,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q)
* needs a pipe control with CS_STALL set beforehand.
* Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
* like the kernel. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0);
@@ -238,7 +238,7 @@ brw_end_query(struct gl_context *ctx, struct gl_query_object *q)
} else {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
- PIPE_CONTROL_WRITE_TIMESTAMP);
+ PIPE_CONTROL_WRITE_TIMESTAMP | (4 - 2));
OUT_RELOC(query->bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE |
@@ -367,7 +367,7 @@ brw_emit_query_begin(struct brw_context *brw)
* needs a pipe control with CS_STALL set beforehand.
* Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
* like the kernel. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0);
@@ -386,7 +386,7 @@ brw_emit_query_begin(struct brw_context *brw)
/* We need to emit depth stall to get the right value for the depth
* count. As a workaround this needs a preceeding pipe control with a
* non-zero post-sync op, the depth count write above does that for us. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -396,7 +396,7 @@ brw_emit_query_begin(struct brw_context *brw)
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_WRITE_DEPTH_COUNT);
+ PIPE_CONTROL_WRITE_DEPTH_COUNT | (4 - 2));
/* This object could be mapped cacheable, but we don't have an exposed
* mechanism to support that. Since it's going uncached, tell GEM that
* we're writing to it. The usual clflush should be all that's required
@@ -438,9 +438,9 @@ brw_emit_query_end(struct brw_context *brw)
* needs a pipe control with CS_STALL set beforehand.
* Workaround: CS_STALL can't be set alone, we pick STALL_AT_SCOREBOARD
* like the kernel. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD);
+ PIPE_CONTROL_STALL_AT_SCOREBOARD | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
@@ -457,7 +457,7 @@ brw_emit_query_end(struct brw_context *brw)
/* We need to emit depth stall to get the right value for the depth
* count. As a workaround this needs a preceeding pipe control with a
* non-zero post-sync op, the depth count write above does that for us. */
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -467,7 +467,7 @@ brw_emit_query_end(struct brw_context *brw)
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_DEPTH_STALL |
- PIPE_CONTROL_WRITE_DEPTH_COUNT);
+ PIPE_CONTROL_WRITE_DEPTH_COUNT | (4 - 2));
OUT_RELOC(brw->query.bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
PIPE_CONTROL_GLOBAL_GTT_WRITE |
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 3392a9f..c562cc7 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -216,7 +216,7 @@ upload_vs_state(struct brw_context *brw)
intel_emit_post_sync_nonzero_flush(intel);
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL |
PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_STATE_CACHE_INVALIDATE);
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
index a1b5ccc..7b82cf2 100644
--- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c
@@ -380,21 +380,21 @@ intel_emit_depth_stall_flushes(struct intel_context *intel)
assert(intel->gen >= 6 && intel->gen <= 7);
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
OUT_BATCH(0); /* address */
OUT_BATCH(0); /* write data */
ADVANCE_BATCH()
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH);
OUT_BATCH(0); /* address */
OUT_BATCH(0); /* write data */
ADVANCE_BATCH();
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL);
OUT_BATCH(0); /* address */
OUT_BATCH(0); /* write data */
@@ -415,7 +415,7 @@ gen7_emit_vs_workaround_flush(struct intel_context *intel)
assert(intel->gen == 7);
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_WRITE_IMMEDIATE);
OUT_RELOC(intel->batch.workaround_bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
@@ -467,7 +467,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
return;
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
OUT_BATCH(0); /* address */
@@ -475,7 +475,7 @@ intel_emit_post_sync_nonzero_flush(struct intel_context *intel)
ADVANCE_BATCH();
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
OUT_RELOC(intel->batch.workaround_bo,
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
@@ -514,7 +514,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
}
BEGIN_BATCH(4);
- OUT_BATCH(_3DSTATE_PIPE_CONTROL);
+ OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
@@ -530,7 +530,7 @@ intel_batchbuffer_emit_mi_flush(struct intel_context *intel)
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_WRITE_FLUSH |
- PIPE_CONTROL_NO_WRITE);
+ PIPE_CONTROL_NO_WRITE | (4 - 2));
OUT_BATCH(0); /* write address */
OUT_BATCH(0); /* write data */
OUT_BATCH(0); /* write data */
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h
index e2a6ee2..2c75a8e 100644
--- a/src/mesa/drivers/dri/intel/intel_reg.h
+++ b/src/mesa/drivers/dri/intel/intel_reg.h
@@ -58,7 +58,7 @@
* PIPE_CONTROL operation, a combination MI_FLUSH and register write with
* additional flushing control.
*/
-#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24) | 2)
+#define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24))
#define PIPE_CONTROL_CS_STALL (1 << 20)
#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19)
#define PIPE_CONTROL_TLB_INVALIDATE (1 << 18)
--
1.7.10.4
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