[Mesa-dev] [PATCH 1/4] i965/blorp: Refactor surface format determination.

[Paul Berry]

This patch moves the responsibility for deciding on the format of the
source and destination surfaces from the
gen{6,7}_blorp_emit_surface_state() functions to
brw_blorp_surface_info::set(), which is shared between Gen6 and Gen7.
This will make it possible to add support for more surface formats
without code duplication.
---
 src/mesa/drivers/dri/i965/brw_blorp.cpp  |    2 ++
 src/mesa/drivers/dri/i965/brw_blorp.h    |    6 ++++++
 src/mesa/drivers/dri/i965/gen6_blorp.cpp |    6 +-----
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |    6 +-----
 4 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 09b176b..d6d00e7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -66,8 +66,10 @@ brw_blorp_surface_info::set(struct intel_mipmap_tree *mt,
        * program swizzle the coordinates.
        */
       this->map_stencil_as_y_tiled = true;
+      this->brw_surfaceformat = BRW_SURFACEFORMAT_R8_UNORM;
    } else {
       this->map_stencil_as_y_tiled = false;
+      this->brw_surfaceformat = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
    }
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h
index c00766c..bff7715 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -90,6 +90,12 @@ public:
     * ARYSPC_LOD0 mode.  Ignored prior to Gen7.
     */
    bool array_spacing_lod0;
+
+   /**
+    * Format that should be used when setting up the surface state for this
+    * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
+    */
+   uint32_t brw_surfaceformat;
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 601bc9b..3e11152 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -426,10 +426,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
    }
    struct intel_region *region = surface->mt->region;
 
-   /* TODO: handle other formats */
-   uint32_t format = surface->map_stencil_as_y_tiled
-      ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-
    uint32_t *surf = (uint32_t *)
       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
                       &wm_surf_offset);
@@ -437,7 +433,7 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
    surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
               BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
               BRW_SURFACE_CUBEFACE_ENABLES |
-              format << BRW_SURFACE_FORMAT_SHIFT);
+              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT);
 
    /* reloc */
    surf[1] = region->bo->offset; /* No tile offsets needed */
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index fe54de8..bf79891 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -150,10 +150,6 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
    }
    struct intel_region *region = surface->mt->region;
 
-   /* TODO: handle other formats */
-   uint32_t format = surface->map_stencil_as_y_tiled
-      ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-
    struct gen7_surface_state *surf = (struct gen7_surface_state *)
       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
                       &wm_surf_offset);
@@ -164,7 +160,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
    if (surface->mt->align_w == 8)
       surf->ss0.horizontal_alignment = 1;
 
-   surf->ss0.surface_format = format;
+   surf->ss0.surface_format = surface->brw_surfaceformat;
    surf->ss0.surface_type = BRW_SURFACE_2D;
    surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
       GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
-- 
1.7.7.6