[Mesa-dev] [PATCH 1/2] radeon/llvm: Lower fpow(A, B) to fexp(mul(B, flog(A))) at DAG level

[Tom Stellard]

On Wed, Oct 17, 2012 at 11:06:28PM +0200, Vincent Lejeune wrote:
> ---
>  lib/Target/AMDGPU/R600ISelLowering.cpp | 12 ++++++++++++
>  lib/Target/AMDGPU/R600ISelLowering.h   |  1 +
>  lib/Target/AMDGPU/R600Instructions.td  |  2 --
>  3 files changed, 13 insertions(+), 2 deletions(-)
>

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

> diff --git a/lib/Target/AMDGPU/R600ISelLowering.cpp b/lib/Target/AMDGPU/R600ISelLowering.cpp
> index da1de57..95294da 100644
> --- a/lib/Target/AMDGPU/R600ISelLowering.cpp
> +++ b/lib/Target/AMDGPU/R600ISelLowering.cpp
> @@ -53,6 +53,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
>    setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
>    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
>    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i1, Custom);
> +  setOperationAction(ISD::FPOW, MVT::f32, Custom);
>  
>    setOperationAction(ISD::ROTL, MVT::i32, Custom);
>  
> @@ -293,6 +294,7 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
>    case ISD::ROTL: return LowerROTL(Op, DAG);
>    case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
>    case ISD::SETCC: return LowerSETCC(Op, DAG);
> +  case ISD::FPOW: return LowerFPOW(Op, DAG);
>    case ISD::INTRINSIC_VOID: {
>      SDValue Chain = Op.getOperand(0);
>      unsigned IntrinsicID =
> @@ -712,6 +714,16 @@ SDValue R600TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const
>    return Cond;
>  }
>  
> +SDValue R600TargetLowering::LowerFPOW(SDValue Op,
> +    SelectionDAG &DAG) const
> +{
> +  DebugLoc DL = Op.getDebugLoc();
> +  EVT VT = Op.getValueType();
> +  SDValue LogBase = DAG.getNode(ISD::FLOG2, DL, VT, Op.getOperand(0));
> +  SDValue MulLogBase = DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), LogBase);
> +  return DAG.getNode(ISD::FEXP2, DL, VT, MulLogBase);
> +}
> +
>  // XXX Only kernel functions are supporte, so we can assume for now that
>  // every function is a kernel function, but in the future we should use
>  // separate calling conventions for kernel and non-kernel functions.
> diff --git a/lib/Target/AMDGPU/R600ISelLowering.h b/lib/Target/AMDGPU/R600ISelLowering.h
> index 1ecdcf3..8bd4859 100644
> --- a/lib/Target/AMDGPU/R600ISelLowering.h
> +++ b/lib/Target/AMDGPU/R600ISelLowering.h
> @@ -61,6 +61,7 @@ private:
>    SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
>    SDValue LowerInputFace(SDNode *Op, SelectionDAG &DAG) const;
>    SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
> +  SDValue LowerFPOW(SDValue Op, SelectionDAG &DAG) const;
>    
>    bool isZero(SDValue Op) const;
>  };
> diff --git a/lib/Target/AMDGPU/R600Instructions.td b/lib/Target/AMDGPU/R600Instructions.td
> index 4ce256d..5b000dc 100644
> --- a/lib/Target/AMDGPU/R600Instructions.td
> +++ b/lib/Target/AMDGPU/R600Instructions.td
> @@ -907,7 +907,6 @@ let Predicates = [isR600] in {
>    def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
>  
>    defm DIV_r600 : DIV_Common<RECIP_IEEE_r600>;
> -  def POW_r600 : POW_Common<LOG_IEEE_r600, EXP_IEEE_r600, MUL, GPRF32>;
>    def SSG_r600 : SSG_Common<CNDGT_r600, CNDGE_r600>;
>    def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>;
>  
> @@ -1008,7 +1007,6 @@ let Predicates = [isEGorCayman] in {
>    defm CUBE_eg : CUBE_Common<0xC0>;
>  
>    defm DIV_eg : DIV_Common<RECIP_IEEE_eg>;
> -  def POW_eg : POW_Common<LOG_IEEE_eg, EXP_IEEE_eg, MUL, GPRF32>;
>    def SSG_eg : SSG_Common<CNDGT_eg, CNDGE_eg>;
>    def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>;
>  
> -- 
> 1.7.11.7
> 
> _______________________________________________
> mesa-dev mailing list
> mesa-dev at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev