[Mesa-dev] [PATCH 2/4] radeon/llvm: SI shader vector instructions implicitly use the EXEC register.

Tom Stellard tom at stellard.net
Thu Sep 6 06:45:52 PDT 2012


On Thu, Sep 06, 2012 at 01:00:01PM +0200, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
>

I'm still not quite sure what the intended use cases are for adding
implicit uses and defs to instructions.  I tried to do this with the VCC
register for VOPC and the V_CNDMASK instructions, but the optimizer
was incorrectly marking some instructions dead.  It's possible there was
something else I was doing that was wrong, but in any case I think we
should keep an eye on this for potential bugs.  Either way, this
change won't hurt anything.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> ---
>  src/gallium/drivers/radeon/SIInstrInfo.td |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/src/gallium/drivers/radeon/SIInstrInfo.td b/src/gallium/drivers/radeon/SIInstrInfo.td
> index 135f279..49ef342 100644
> --- a/src/gallium/drivers/radeon/SIInstrInfo.td
> +++ b/src/gallium/drivers/radeon/SIInstrInfo.td
> @@ -99,6 +99,7 @@ def SMRDmemri : Operand<iPTR> {
>  def ADDR_Reg     : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
>  def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
>  
> +let Uses = [EXEC] in {
>  def EXP : Enc64<
>    (outs),
>    (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
> @@ -244,6 +245,7 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
>    let usesCustomInserter = 1;
>    let neverHasSideEffects = 1;
>  }
> +} // End Uses = [EXEC]
>  
>  class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
>      Enc32<outs, ins, asm, pattern> {
> @@ -337,6 +339,7 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
>  }
>      
>  
> +let Uses = [EXEC] in {
>  class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
>      Enc32 <outs, ins, asm, pattern> {
>  
> @@ -430,6 +433,7 @@ class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
>    let PostEncoderMethod = "VOPPostEncode";
>    let DisableEncoding = "$dst";
>  }
> +} // End Uses = [EXEC]
>  
>  class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
>    op,
> -- 
> 1.7.10.4
> 
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