[Mesa-dev] [PATCH 1/2] i965/vs: Add a function to fix-up uniform arguments for 3-src insts.

[Chris Forbes]

Both patches are

Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>

On Fri, Apr 26, 2013 at 6:51 AM, Matt Turner <mattst88 at gmail.com> wrote:
> Three-source instructions have a vertical stride overloaded to 4, which
> prevents directly using vec4 uniforms as arguments. Instead we need to
> insert a MOV instruction to do the replication for the three-source
> instruction.
>
> With this in place, we can use three-source instructions in the vertex
> shader. While some thought needs to go into deciding whether its better
> to use a three-source instruction rather than a sequence of equivalent
> instructions (when one or more sources are uniforms or immediates), this
> will allow us to skip a lot of ugly lowering code and use the BFE and
> BFI2 instructions directly.
> ---
> These patches should go before my ARB_gpu_shader5 series, and allow me to
> drop
>
> [PATCH 07/16] glsl: Add bitfieldInsert-to-bfm/bitops lowering pass.
> [PATCH 08/16] glsl: Add BFE-to-bitops lowering pass.
>
>  src/mesa/drivers/dri/i965/brw_vec4.h           |  2 ++
>  src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23 +++++++++++++++++++++++
>  2 files changed, 25 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 697ab86..c280922 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -430,6 +430,8 @@ public:
>     void emit_scs(ir_instruction *ir, enum prog_opcode op,
>                  dst_reg dst, const src_reg &src);
>
> +   src_reg fix_3src_operand(src_reg src);
> +
>     void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
>     void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
>     void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index 2fb8482..69e805d 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -224,6 +224,29 @@ vec4_visitor::emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements
>  }
>
>  src_reg
> +vec4_visitor::fix_3src_operand(src_reg src)
> +{
> +   /* Using vec4 uniforms in SIMD4x2 programs is difficult. You'd like to be
> +    * able to use vertical stride of zero to replicate the vec4 uniform, like
> +    *
> +    *    g3<0;4,1>:f - [0, 4][1, 5][2, 6][3, 7]
> +    *
> +    * But you can't, since vertical stride is always four in three-source
> +    * instructions. Instead, insert a MOV instruction to do the replication so
> +    * that the three-source instruction can consume it.
> +    */
> +
> +   /* The MOV is only needed if the source is a uniform or immediate. */
> +   if (src.file != UNIFORM && src.file != IMM)
> +      return src;
> +
> +   dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
> +   expanded.type = src.type;
> +   emit(MOV(expanded, src));
> +   return src_reg(expanded);
> +}
> +
> +src_reg
>  vec4_visitor::fix_math_operand(src_reg src)
>  {
>     /* The gen6 math instruction ignores the source modifiers --
> --
> 1.8.1.5
>