[Mesa-dev] [PATCH 3/3] i965/gen7: Don't use L3$ for render targets

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

According to HSW Bspec L3$ evictions may land in LLC regardless of
LLC MOCS/PTE settings. That means we shouldn't set scanout buffers
as L3 cacheable when writing to them.

So far I've been unable to observe this phenomenon on my IVB, but
better safe than sorry. Especially since this doesn't appear to
hurt performance.

Ideally this should be limited to scanout buffers, but that information
is not availabe to Mesa. Limiting it to winsys buffers might be a
reasonable comporomise, but MOCS setup appears to be done at a
lower layer where that information is already lost, and I was too
lazy to start passing that infromation down.

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 3 ++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a9d6198..6f34c8d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -143,7 +143,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
     */
    struct intel_region *region = surface->mt->region;
    uint32_t tile_x, tile_y;
-   uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
+   /* FIXME use L3$ for non-scanout render targets */
+   uint8_t mocs = !is_render_target && brw->gen == 7 ? GEN7_MOCS_L3 : 0;
 
    uint32_t tiling = surface->map_stencil_as_y_tiled
       ? I915_TILING_Y : region->tiling;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index cd83daf..f7447cb 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -514,7 +514,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    bool is_array = false;
    int depth = MAX2(rb->Depth, 1);
    int min_array_element;
-   uint8_t mocs = brw->gen == 7 ? GEN7_MOCS_L3 : 0;
+   /* FIXME use L3$ for non-scanout renderbuffers */
+   uint8_t mocs = 0;
    GLenum gl_target = rb->TexImage ?
                          rb->TexImage->TexObject->Target : GL_TEXTURE_2D;
 
-- 
1.8.1.5