[Mesa-dev] [PATCH 3/3] i965/gen7: Don't use L3$ for render targets

[Chad Versace]

On 08/12/2013 06:07 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> According to HSW Bspec L3$ evictions may land in LLC regardless of
> LLC MOCS/PTE settings. That means we shouldn't set scanout buffers
> as L3 cacheable when writing to them.
>
> So far I've been unable to observe this phenomenon on my IVB, but
> better safe than sorry. Especially since this doesn't appear to
> hurt performance.
>
> Ideally this should be limited to scanout buffers, but that information
> is not availabe to Mesa. Limiting it to winsys buffers might be a
> reasonable comporomise, but MOCS setup appears to be done at a
> lower layer where that information is already lost, and I was too
> lazy to start passing that infromation down.

Let's try harder to add that plumbing. I'll try to think of something tomorrow.