[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

[Chad Versace]

On 08/12/2013 06:07 AM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
> so let's make use of it.
>
> pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
> other things show less gains/no regressions, except furmark which
> loses some 10 points.
>
> I didn't have a BYT at hand for testing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>   src/mesa/drivers/dri/i965/brw_draw_upload.c       | 2 +-
>   src/mesa/drivers/dri/i965/brw_misc_state.c        | 2 +-
>   src/mesa/drivers/dri/i965/gen6_blorp.cpp          | 4 ++--
>   src/mesa/drivers/dri/i965/gen7_blorp.cpp          | 6 +++---
>   src/mesa/drivers/dri/i965/gen7_misc_state.c       | 2 +-
>   src/mesa/drivers/dri/i965/gen7_vs_state.c         | 2 +-
>   src/mesa/drivers/dri/i965/gen7_wm_state.c         | 2 +-
>   src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 ++--
>   8 files changed, 12 insertions(+), 12 deletions(-)

Conceptually, the patch looks good. The (intel->gen == 7)
checks should be removed from the changes in the gen7 files.